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LPC11U24FHN33 PDF预览

LPC11U24FHN33

更新时间: 2024-09-25 11:39:11
品牌 Logo 应用领域
恩智浦 - NXP 闪存微控制器静态存储器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
67页 1196K
描述
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up to 10 kB SRAM and 4 kB EEPROM; USB device; USART

LPC11U24FHN33 数据手册

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LPC11U2x  
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up  
to 10 kB SRAM and 4 kB EEPROM; USB device; USART  
Rev. 1 — 29 November 2011  
Preliminary data sheet  
1. General description  
The LPC11U2x are a ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for  
8/16-bit microcontroller applications, offering performance, low power, simple instruction  
set and memory addressing together with reduced code size compared to existing 8/16-bit  
architectures.  
The LPC11U2x operate at CPU frequencies of up to 50 MHz.  
Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the  
LPC11U2x brings unparalleled design flexibility and seamless integration to today’s  
demanding connectivity solutions.  
The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to  
10 kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I2C-bus interface,  
one RS-485/EIA-485 USART with support for synchronous mode and smart card  
interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC  
(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.  
2. Features and benefits  
System:  
ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.  
ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).  
Non-Maskable Interrupt (NMI) input selectable from several input sources.  
System tick timer.  
Memory:  
Up to 32 kB on-chip flash program memory.  
Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.  
Up to 10 kB SRAM data memory.  
16 kB boot ROM.  
In-System Programming (ISP) and In-Application Programming (IAP) for flash and  
EEPROM via on-chip bootloader software.  
ROM-based USB drivers. Flash updates via USB supported.  
ROM-based 32-bit integer division routines.  
Debug options:  
Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan  
Description Language).  
Serial Wire Debug.  

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