Datasheet > LP87C51FA16

LP87C51FA16

更新时间： 2024-02-09 04:18:07

品牌	Logo	应用领域
英特尔 - INTEL		可编程只读存储器微控制器光电二极管
页数	文件大小	规格书
18页	254K
描述
Microcontroller, 8-Bit, OTPROM, 16MHz, CMOS, PDIP40, PLASTIC, DIP-40

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LP87C51FA16 数据手册

AUTOMOTIVE 87C51FA/FB/FC/FC-20

To drive the device from an external clock source,

XTAL1 should be driven, while XTAL2 floats, as

shown in Figure 5. There are no requirements on the

duty cycle of the external clock signal, since the in-

put to the internal clocking circuitry is through a di-

vide-by-two flip-flop, but minimum and maximum

high and low times specified on the data sheet must

be observed.

IDLE MODE

The user’s software can invoke the Idle Mode. When

the microcontroller is in this mode, power consump-

tion is reduced. The Special Function Registers and

the onboard RAM retain their values during Idle, but

the processor stops executing instructions. Idle

Mode will be exited if the chip is reset or if an en-

abled interrupt occurs. The PCA timer/counter can

optionally be left running or paused during Idle

Mode.

An external oscillator may encounter as much as

100 pF load at XTAL1 when it starts up. This is due

to interaction between the amplifier and its feedback

capacitance. Once the external signal meets V and

specifications the capacitance will not exceed

20 pF.

POWER DOWN MODE

To save even more power, a Power Down mode can

be invoked by software. In this mode, the oscillator

is stopped and the instruction that invoked Power

Down is the last instruction executed. The on-chip

RAM and Special Function Registers retain their val-

ues until the Power Down mode is terminated.

On the 87C51FA/FB/FC either a hardware reset or

external interrupt can cause an exit from Power

Down. Reset redefines all the SFRs but does not

change the on-chip RAM. An external interrupt al-

lows both the SFRs and the on-chip RAM to retain

their values.

270961–5

30 pF 10 pF for Crystals

C1, C2

For Ceramic Resonators, contact resonator manufac-

turer.

To properly terminate Power Down the reset or ex-

ternal interrupt should not be executed before V is

Figure 4. Oscillator Connections

restored to its normal operating level and must be

held active long enough for the oscillator to restart

and stabilize (normally less than 10 ms).

With an external interrupt. INT0 or INT1 must be en-

abled and configured as level-sensitive. Holding the

pin low restarts the oscillator (the oscillator must be

allowed time to stabilize after start up, before this pin

is released high) but bringing the pin back high com-

pletes the exit. Once the interrupt is serviced, the

next instruction to be executed after RETI will be the

one following the instruction that put the device into

Power Down.

270961–6

Figure 5. External Clock Drive Configuration

1...3 4 567 8 9...18

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