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LNK364GN PDF预览

LNK364GN

更新时间: 2024-02-26 10:24:08
品牌 Logo 应用领域
帕沃英蒂格盛 - POWERINT 开关
页数 文件大小 规格书
16页 736K
描述
Energy Effi cient, Low Power Off-Line Switcher IC

LNK364GN 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:DIP包装说明:DIP,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:14 weeks风险等级:1.69
其他特性:REQUIRES AN AC SUPPLY OF 85 TO 265 V模拟集成电路 - 其他类型:SWITCHING REGULATOR
控制技术:PULSE WIDTH MODULATIONJESD-30 代码:R-PDIP-T7
JESD-609代码:e3长度:9.575 mm
功能数量:1端子数量:7
最高工作温度:125 °C最低工作温度:-40 °C
最大输出电流:0.4 A封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified表面贴装:NO
切换器配置:SINGLE最大切换频率:140 kHz
温度等级:AUTOMOTIVE端子面层:PURE MATTE TIN
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

LNK364GN 数据手册

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LNK362-364  
Input Filter  
Capacitor  
TOP VIEW  
Y1-  
Capacitor  
FB  
D
T
r
a
n
s
f
o
r
m
e
r
BP  
S
S
+
-
HV DC  
INPUT  
S
S
CBP  
Opto-  
coupler  
+
DC  
Maximize hatched copper  
OUT  
areas (  
) for optimum  
-
heatsinking  
Output Filter  
Capacitor  
PI-4155-102705  
Figure 6. Recommended Printed Circuit Layout for LinkSwitch-XT in a Flyback Converter Conguration.  
LinkSwitch-XT Layout Considerations  
(~200 V) and diode clamp across the primary winding. In all  
cases, to minimize EMI, care should be taken to minimize the  
circuit path from the clamp components to the transformer and  
LinkSwitch-XT.  
See Figure 6 for a recommended circuit board layout for  
LinkSwitch-XT.  
Single Point Grounding  
Thermal Considerations  
Use a single point ground connection from the input lter  
capacitor to the area of copper connected to the SOURCE  
pins.  
The copper area underneath the LinkSwitch-XT acts not only  
as a single point ground, but also as a heatsink. As this area is  
connected to the quiet source node, it should be maximized for  
good heat sinking of LinkSwitch-XT. The same applies to the  
cathode of the output diode.  
Bypass Capacitor CBP  
TheBYPASSpincapacitorshouldbelocatedasnearaspossible  
to the BYPASS and SOURCE pins.  
Y Capacitor  
The placement of the Y capacitor should be directly from  
the primary input lter capacitor positive terminal to the  
common/return terminal of the transformer secondary. Such  
a placement will route high magnitude common-mode surge  
currents away from the LinkSwitch-XT device. Note that if an  
input pi (C, L, C) EMI lter is used, then the inductor in the  
lter should be placed between the negative terminals of the  
input lter capacitors.  
Primary Loop Area  
The area of the primary loop that connects the input lter  
capacitor, transformer primary and LinkSwitch-XT together  
should be kept as small as possible.  
Primary Clamp Circuit  
Aclamp is used to limit peak voltage on the DRAIN pin at turn  
off. This can be achieved by using an RCD clamp or a Zener  
C
12/05  
6

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