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LMV115MG PDF预览

LMV115MG

更新时间: 2024-01-26 17:42:25
品牌 Logo 应用领域
美国国家半导体 - NSC 振荡器GSM
页数 文件大小 规格书
13页 473K
描述
GSM Baseband 30MHz 2.8V Oscillator Buffer

LMV115MG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:TSSOP, TSSOP6,.08针数:6
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.84
Is Samacsys:N放大器类型:BUFFER
标称带宽 (3dB):9 MHzJESD-30 代码:R-PDSO-G6
JESD-609代码:e3长度:2 mm
湿度敏感等级:1负供电电压上限:
标称负供电电压 (Vsup):功能数量:1
端子数量:6最高工作温度:85 °C
最低工作温度:-40 °C最小输出电流:0.1 A
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP6,.08封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:2.8 V认证状态:Not Qualified
座面最大高度:1.1 mm标称压摆率:18 V/us
子类别:Buffer Amplifiers最大压摆率:0.52 mA
供电电压上限:3.6 V标称供电电压 (Vsup):2.8 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:1.25 mm
Base Number Matches:1

LMV115MG 数据手册

 浏览型号LMV115MG的Datasheet PDF文件第7页浏览型号LMV115MG的Datasheet PDF文件第8页浏览型号LMV115MG的Datasheet PDF文件第9页浏览型号LMV115MG的Datasheet PDF文件第11页浏览型号LMV115MG的Datasheet PDF文件第12页浏览型号LMV115MG的Datasheet PDF文件第13页 
Application Section  
GENERAL  
The LMV115 is specially designed to minimize the effects of  
spurious signals from the base band chip to the oscillator.  
Beside this the influence of varying load resistance and  
capacitance to the oscillator is minimized, while increasing  
the drive capability. The input of the LMV115 is internally  
biased with two equal resistors to the power supply rails, and  
makes AC coupling possible without external bias resistors  
at the input. The LMV115 has excellent gain phase margin.  
The LMV115 offers a shutdown pin that can be used to  
disable the device in order to optimize current consumption  
and also has a feature to control the supply voltage to an  
external oscillator. When the shutdown pin is connected to  
VDD the device is in shutdown mode.  
SWITCHED POWER SUPPLY CONNECTION  
The LMV115 features an enable/disable function for an ex-  
ternal oscillator by controlling its supply voltage (pin 4). See  
also the schematic diagram on the front page. During normal  
operating mode, pin 4 is connected to the positive supply rail  
via an internal switch. The resistance between the positive  
supply rail and pin 4, RON, is specified in the electrical  
characterization table. Oscillators with a supply current up to  
several milliamps can easily be powered from pin 4. During  
shutdown, pin 4 is switched to the negative supply rail. The  
simplified schematic for this part of the device is shown in  
Figure 1  
20075132  
FIGURE 2. Dual Supply Mode  
PSRR  
If an AC signal is applied to one of the supply lines, while the  
input is floating, the signal at the input pin is half the signal at  
the supply line, causing the same signal at the output of the  
buffer. This will result in a PSRR of only 6dB (see Figure 2).  
In a typical application the input is driven from a low ohmic  
source that means the disturbance at the supply lines is  
attenuated by the series resistors of 110k and the source  
impedance. In case the buffer is connected to a 50source,  
the resulting suppression will be 20*log [(R1 + RBIAS)/RBIAS  
]
= 67dB for signals at the supply line. The PSRR can also be  
measured correctly for this type of input by shorten the input  
to mid-supply. Due to the internal structure it is not recom-  
mended to measure with the input connected to ground. To  
measure correctly the PSRR, two signals are applied to both  
VDD and VEE but with 180˚ phase difference (see Figure 2).  
In this case, both signals are subtracted and there will be no  
signal at the input. The resulting disturbance at the output is  
now only caused by the signals at the supply lines.  
INPUT AND OUTPUT LEVEL  
Due to the internal loop gain of 1, the output will follow the  
input. The output voltage cannot swing as close to the supply  
rail as the input voltage. For linear operation the input volt-  
age swing should not exceed the output voltage swing. The  
restrictions for the output voltage can be examined by the  
two curves in Figure 3. The curve VOUT (V) shows the  
response of the output signal versus the input signal and the  
curve VOUT – VIN (V) shows the difference between the  
output and the input signal.  
20075131  
FIGURE 1. Supply For External Oscillator  
INPUT CONFIGURATION  
The input of the LMV115 is internally biased at mid-supply by  
a divider of two equal resistors. With the LMV115 in shut-  
down mode, the internal resistor connected to the VDD is  
shortened to the negative power supply rail via a switch. This  
makes the power consumption in ‘off’ mode almost zero, but  
causes a small difference for the input impedance between  
the on and off modes. Both resistors are 110kso the  
resulting input impedance will be approximately 55k. The  
input configuration allows AC coupling on the input of the  
LMV115. A simplified schematic of the input is shown in  
Figure 2.  
www.national.com  
10  

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