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LMC1992CCN PDF预览

LMC1992CCN

更新时间: 2024-01-14 20:01:27
品牌 Logo 应用领域
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页数 文件大小 规格书
14页 261K
描述
LMC1992 Digitally-Controlled Stereo Tone and Volume Circuit with Four-Channel Input-Selector

LMC1992CCN 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP28,.6Reach Compliance Code:unknown
风险等级:5.92JESD-30 代码:R-PDIP-T28
JESD-609代码:e0端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP28,.6封装形状:RECTANGULAR
封装形式:IN-LINE电源:8 V
认证状态:Not Qualified子类别:Audio Control ICs
表面贴装:NO技术:BICMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

LMC1992CCN 数据手册

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Applications Information (Continued)  
SERIAL COMMUNICATION INTERFACE  
Figure 5 shows the LMC1992’s timing diagram for its three  
wire MICROWIRE interface. A controller’s data stream can  
be any length; once the correct device address is received  
by the LMC1992, any number of data bits can be sent; the  
last nine bits occurring before ENABLE goes high are used  
by the LMC1992. The first two bits in a valid data stream are  
decoded and used as device address bits. The LMC1992  
uses a unique address of 1,0. The LMC1992 will not re-  
spond to information on the DATA line if any other address  
is used. This allows other MICROWIRE serially programma-  
ble devices to share the same three-wire communication  
bus. When ENABLE goes high, any further serial data is  
ignored and the contents of the shift register is transferred  
to the data latches. Only when information is received by  
the data latches do any function or setting changes take  
place. The first three of nine bits select one of the  
LMC1992s functions. The remaining six bits set the select-  
ed function to the desired value or position.  
TL/H/1078922  
A data bit is accepted as valid and clocked into an internal  
shift register on each rising edge of the signal appearing at  
the LMC1992s CLOCK input pin. Proper data interpretation  
and operation is ensured when ENABLE makes its falling  
transition during the time when CLOCK is low. Erroneous  
operation will result if the ENABLE signal makes its falling  
transition at any other time.  
FIGURE 4. The Tone Control Amplifier  
Increasing the values of C2 and C3 decreases the turnover  
and inflection frequencies: i.e., the Tone Control Response  
Curves shown in Typical Performance Curves will shift left  
when C2 and C3 are increased and shift right when C2 and  
e
e
0.0082, 2 dB steps are  
C3 are decreased. With C2  
C3  
achieved at 100 Hz and 10 kHz. Changing C2 and C3 to  
0.01 mF shifts the 2 dB per step frequency to 72 Hz and 8.3  
kHz. If the tone control capacitors’ size is decreased these  
e
dB steps take place at 130 Hz and 11.2 kHz.  
e
0.0068 mF the 2  
frequencies will increase. With C2  
C3  
FADER FUNCTION  
The four fader functions are all independently adjustable  
and therefore no balance control is needed. Emulating a  
balance control is accomplished through software by simul-  
taneously changing a channel’s front and rear faders by  
equal amounts. To satisfy normal balance requirements the  
faders have an attenuation range of 40 dB.  
TL/H/1078921  
Note 1: Negative transition on ENABLE clears previous address. Clock must be low during transition.  
Note 2: Additional don’t care states may be inserted here for ease of programming. (Optional.)  
Note 3: Positive transition on ENABLE latches in new data if the LMC1992 has been addressed. Clock can either be high or low during transition.  
FIGURE 5. Clocking Data into the Standard MICROWIRE Interface  
(Minimum Number of Bits in Data Stream)  
9

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