LH5PV16256
CMOS 4M (256K × 16) Pseudo-Static RAM
FEATURES
DESCRIPTION
The LH5PV16256 is a 4M bit Pseudo-Static RAM with
a 262,144 words × 16 bit organization.
• 262,144 words × 16 bit organization
• Power supply: +3.0 ± 0.15 V
• Access time: 120 ns (MAX.)
• Cycle time: 190 ns (MIN.)
PIN CONNECTIONS
44-PIN TSOP (Type II)
TOP VIEW
• Power consumption (MAX.):
126 mW (Operating)
44
43
LWE
1
GND
I/O15
2
UWE
A0
94.5 µW (Standby = CMOS input level)
220.5 µW
(Self-refresh = CMOS input level)
3
4
42
41
40
I/O14
I/O13
I/O12
A1
A2
5
39
38
I/O11
I/O10
A3
A4
6
7
• LVTTL compatible I/O
A5
A6
8
9
37
36
35
34
I/O9
I/O8
VCC
VCC
• Available for address refresh,
auto-refresh, and self-refresh modes
A17
CS
A16
A15
A14
10
11
12
13
14
15
16
17
• 2,048 refresh cycles/32 ms
• Address non-multiple
33
32
31
RFSH
I/O7
I/O6
I/O5
I/O4
I/O3
• Available for byte write mode using UWE
A13
A12
A11
A10
A9
30
29
and LWE pins
• Package:
28
44-pin, TSOP (Type II)
18
19
27
26
25
I/O2
I/O1
I/O0
• Process: Silicon-gate CMOS
A8
20
24
23
OE
• Operating temperature: 0 - 70°C
A7
21
22
CE
GND
• Not designed or rated as radiation
5PV16256S-1
hardened
Figure 1. Pin Connections
1