Philips Semiconductors Linear Products
Product specification
Sample-and-hold amplifiers
LF198/LF298/LF398
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following conditions apply: unit is in “sample” mode; V = ±15V; T = 25°C; -11.5V3 V ≤ +11.5V; C =0.01µF;
S
J
IN
H
and R = 10kΩ. Logic reference voltage = 0V and logic voltage = 2.5V.
L
LF198/LF298
LF398
Typ
2
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
Typ
Max
Min
Max
7
T =25°C
J
1
3
5
4
V
OS
Input offset voltage
mV
Full temperature range
10
T =25°C
5
25
75
10
50
J
4
I
Input bias current
nA
BIAS
Full temperature range
100
10
10
Input impedance
Gain error
T =25°C
10
10
Ω
J
0.002 0.005
0.02
0.004 0.01
0.02
T =25°C, RL=10k
Full temperature range
J
%
dB
Ω
Feedthrough attenuation
ratio at 1kHz
86
96
80
90
T =25°C, C =0.01µF
J
h
0.5
2
0.5
4
T =25°C, “HOLD“ mode
J
Output impedance
Full temperature range
4
6
2
“HOLD“ step
T =25°C, C =0.01µF, V =0
OUT
0.5
4.5
2.0
5.5
1.0
4.5
2.5
6.5
mV
mA
J
h
4
I
t
Supply current
T ≤ 25°C
J
CC
Logic and logic reference
input current
T = 25°C
2
10
2
10
µA
J
Leakage current into hold
T =25°C, “HOLD“ mode
30
100
30
200
pA
J
4
capacitor
∆V
=10V, C =1000pF
4
4
OUT
h
Acquisition time to 0.1%
µs
AC
C =0.01µF
h
20
20
Hold capacitor charging
current
V -V =2V
IN OUT
5
5
mA
Supply voltage rejection
ratio
V
=0
80
110
1.4
80
110
1.4
dB
V
OUT
Differential logic threshold
T =25°C
J
0.8
2.4
0.8
2.4
NOTES:
1. Unless otherwise specified, the following conditions apply. Unit is in “sample“ mode, V =±15V, T =25°C, -11.5V ≤ V ≤ +11.5V, C = 0.01µF,
S
J
IN
h
and R = 10kΩ. Logic reference voltage = 0V and logic voltage = 2.5V.
L
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an
additional 0.5mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold
capacitor value.
3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated
ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input
signal range.
4. The parameters are guaranteed over a supply voltage of ±5 to ±18V.
881
August 31, 1994