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LF398N

更新时间: 2024-02-12 23:18:49
品牌 Logo 应用领域
恩智浦 - NXP 放大器
页数 文件大小 规格书
5页 133K
描述
Sample-and-hold amplifiers

LF398N 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.33.00.01风险等级:5.64
最长采集时间:6 µs放大器类型:SAMPLE AND HOLD CIRCUIT
JESD-30 代码:R-PDSO-GJESD-609代码:e0
功能数量:1封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
采样并保持/跟踪并保持:SAMPLE子类别:Sample and Hold Circuit
表面贴装:YES端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子位置:DUAL
Base Number Matches:1

LF398N 数据手册

 浏览型号LF398N的Datasheet PDF文件第1页浏览型号LF398N的Datasheet PDF文件第2页浏览型号LF398N的Datasheet PDF文件第4页浏览型号LF398N的Datasheet PDF文件第5页 
Philips Semiconductors Linear Products  
Product specification  
Sample-and-hold amplifiers  
LF198/LF298/LF398  
DC ELECTRICAL CHARACTERISTICS  
Unless otherwise specified, the following conditions apply: unit is in “sample” mode; V = ±15V; T = 25°C; -11.5V3 V +11.5V; C =0.01µF;  
S
J
IN  
H
and R = 10k. Logic reference voltage = 0V and logic voltage = 2.5V.  
L
LF198/LF298  
LF398  
Typ  
2
SYMBOL  
PARAMETER  
TEST CONDITIONS  
UNIT  
Min  
Typ  
Max  
Min  
Max  
7
T =25°C  
J
1
3
5
4
V
OS  
Input offset voltage  
mV  
Full temperature range  
10  
T =25°C  
5
25  
75  
10  
50  
J
4
I
Input bias current  
nA  
BIAS  
Full temperature range  
100  
10  
10  
Input impedance  
Gain error  
T =25°C  
10  
10  
J
0.002 0.005  
0.02  
0.004 0.01  
0.02  
T =25°C, RL=10k  
Full temperature range  
J
%
dB  
Feedthrough attenuation  
ratio at 1kHz  
86  
96  
80  
90  
T =25°C, C =0.01µF  
J
h
0.5  
2
0.5  
4
T =25°C, “HOLD“ mode  
J
Output impedance  
Full temperature range  
4
6
2
“HOLD“ step  
T =25°C, C =0.01µF, V =0  
OUT  
0.5  
4.5  
2.0  
5.5  
1.0  
4.5  
2.5  
6.5  
mV  
mA  
J
h
4
I
t
Supply current  
T 25°C  
J
CC  
Logic and logic reference  
input current  
T = 25°C  
2
10  
2
10  
µA  
J
Leakage current into hold  
T =25°C, “HOLD“ mode  
30  
100  
30  
200  
pA  
J
4
capacitor  
V  
=10V, C =1000pF  
4
4
OUT  
h
Acquisition time to 0.1%  
µs  
AC  
C =0.01µF  
h
20  
20  
Hold capacitor charging  
current  
V -V =2V  
IN OUT  
5
5
mA  
Supply voltage rejection  
ratio  
V
=0  
80  
110  
1.4  
80  
110  
1.4  
dB  
V
OUT  
Differential logic threshold  
T =25°C  
J
0.8  
2.4  
0.8  
2.4  
NOTES:  
1. Unless otherwise specified, the following conditions apply. Unit is in “sample“ mode, V =±15V, T =25°C, -11.5V V +11.5V, C = 0.01µF,  
S
J
IN  
h
and R = 10k. Logic reference voltage = 0V and logic voltage = 2.5V.  
L
2. Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1pF, for instance, will create an  
additional 0.5mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold  
capacitor value.  
3. Leakage current is measured at a junction temperature of 25°C. The effects of junction temperature rise due to power dissipation or elevated  
ambient can be calculated by doubling the 25°C value for each 11°C increase in chip temperature. Leakage is guaranteed over full input  
signal range.  
4. The parameters are guaranteed over a supply voltage of ±5 to ±18V.  
881  
August 31, 1994  

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