Datasheet > LF298MX

LF298MX

更新时间： 2024-01-17 22:41:47

品牌	Logo	应用领域
美国国家半导体 - NSC		放大器光电二极管
页数	文件大小	规格书
13页	519K
描述
IC SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, PDSO14, SOIC-14, Sample and Hold Circuit

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LF298MX 技术参数

生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	SOP-14	针数：	14
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.13
最长采集时间：	25 µs	标称采集时间：	20 µs
放大器类型：	SAMPLE AND HOLD CIRCUIT	最大模拟输入电压：	11.5 V
最小模拟输入电压：	-11.5 V	JESD-30 代码：	R-PDSO-G14
JESD-609代码：	e0	长度：	8.6235 mm
湿度敏感等级：	1	负供电电压上限：	-18 V
标称负供电电压 (Vsup)：	-15 V	功能数量：	1
端子数量：	14	最高工作温度：	85 °C
最低工作温度：	-25 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP14,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
包装方法：	TR	峰值回流温度（摄氏度）：	235
电源：	+-15 V	认证状态：	Not Qualified
采样并保持/跟踪并保持：	SAMPLE	座面最大高度：	1.753 mm
子类别：	Sample and Hold Circuit	最大压摆率：	5.5 mA
供电电压上限：	18 V	标称供电电压 (Vsup)：	15 V
表面贴装：	YES	技术：	BIPOLAR
温度等级：	OTHER	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	3.9 mm	Base Number Matches：	1

LF298MX 数据手册

Application Hints (Continued)

Guarding Technique

logic input for signal delay, calculate the slope of the wave-

form at the threshold point to ensure that it is at least

1.0 V/µs.

Sampling Dynamic Signals

Sample error to moving input signals probably causes more

confusion among sample-and-hold users than any other pa-

rameter. The primary reason for this is that many users make

the assumption that the sample and hold amplifier is truly

locked on to the input signal while in the sample mode. In ac-

tuality, there are finite phase delays through the circuit creat-

ing an input-output differential for fast moving signals. In ad-

dition, although the output may have settled, the hold

capacitor has an additional lag due to the 300Ω series resis-

tor on the chip. This means that at the moment the “hold”

command arrives, the hold capacitor voltage may be some-

what different than the actual analog input. The effect of

these delays is opposite to the effect created by delays in the

logic which switches the circuit from sample to hold. For ex-

ample, consider an analog input of 20 Vp-p at 10 kHz. Maxi-

mum dV/dt is 0.6 V/µs. With no analog phase delay and 100

ns logic delay, one could expect up to (0.1 µs) (0.6V/µs)

= 60 mVerror if the “hold” signal arrived near maximum dV/dt

of the input. A positive-going input would give a +60 mV er-

ror. Now assume a 1 MHz (3 dB) bandwidth for the overall

analog loop. This generates a phase delay of 160 ns. If the

hold capacitor sees this exact delay, then error due to analog

delay will be (0.16 µs) (0.6 V/µs) = −96 mV. Total output error

is +60 mV (digital) −96 mV (analog) for a total of −36 mV. To

add to the confusion, analog delay is proportioned to hold

capacitor value while digital delay remains constant. A family

of curves (dynamic sampling error) is included to help esti-

mate errors.

DS005692-5

Use 10-pin layout. Guard around C_his tied to output.

A curve labeled Aperture Time has been included for sam-

pling conditions where the input is steady during the sam-

pling period, but may experience a sudden change nearly

coincident with the “hold” command. This curve is based on

a 1 mV error fed into the output.

A second curve, Hold Settling Time indicates the time re-

quired for the output to settle to 1 mV after the “hold” com-

mand.

Digital Feedthrough

Fast rise time logic signals can cause hold errors by feeding

externally into the analog input at the same time the amplifier

is put into the hold mode. To minimize this problem, board

layout should keep logic lines as far as possible from the

analog input and the C_hpin. Grounded guarding traces may

also be used around the input line, especially if it is driven

from a high impedance source. Reducing high amplitude

logic signals to 2.5V will also help.

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LF298MX/NOPB	NSC	IC SAMPLE AND HOLD AMPLIFIER, 20 us ACQUISITION TIME, PDSO14, ROHS COMPLIANT, SOIC-14, Sam	获取价格
LF298MX/NOPB	TI	Monolithic Sample-and-Hold Circuits	获取价格
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