LDC5072-Q1
ZHCSJ59C –DECEMBER 2018 –REVISED JULY 2023
www.ti.com.cn
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
over recommended Vcc range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input Supply
VCCRamp
Allowed VCC ramp up rate
0.17
80
100e6
V/s
nF
CEXT_VCC
External VCC decoupling capacitor range
100
3.3
Internal LDO Regulator VREG
VVREG
Internal LDO output voltage
3.15
2.91
3.6
VPOR_VREG_UTH
VPOR_VREG_LTH
VREG power-on upper threshold
VREG power-on lower thershold
3.15
V
Maximum external load on VREG (used
for setting voltage on AGC_EN pin
externally) (Information Only)
ILOAD_REG_EXT
1
mA
nF
ILIM_VREG
VREG current limit
40
90
CEXT_VREG
Signal Path
External VREG decoupling capacitor
180
2000
Integral Non-Linearity error(3) of the signal
path transfer function for each channel
measured as:
For static inputs; VCC=5V;
ErrINL
Maximum % deviation of output from a
best fit line through measured outputs
when input is swept from minium to
maximum value.
-3.5V ≤( VOUTxP-VOUTxN
≤3.5V
)
1%
2.5
%
Propagation Delay through receive stage Measured as zero crossing
3.3
3
4.6
5
at room temperature.
of diffrential input (INx) to
zero crossing of differential
output (OUTx)
tPROP_CH
μs
Propagation Delay through receive stage
across temperature (-40℃to 160℃).
COUT on each pin = 10nF
Measured as delay
between the zero crossings
of the diffrential outputs.
Propagation Delay difference between two
channels across temperature
tPROP_DIFF
500
65
ns
Measured for static inputs
only for VCC=5V; -1.75V ≤
( VOUT0P-VOUT1P) ≤1.75V
Difference between single ended outputs
calculated at VOUT0P-VOUT1P
VOUT_SE
50
mV
Difference between differential output
VOUT_DIFF
calculated as (VOUT0P-VOUT0N) - (VOUT1P
-
100
VOUT1N) at room temperature
Measured for static inputs
Deviation of VOUT_DIFF at -40℃from room only for VCC=5V; -3.5V ≤
mV
20
38
temperature
( VOUTxP-VOUTxN) ≤3.5V
VOUT_DIFF_TC
Deviation of VOUT_DIFF at 160℃from room
temperature
Fixed Gain Mode;
VCC=3.3V 4.55%VREG <
VAGC_EN < 95.45%VREG
-40℃≤TA ≤160°C
-0.4
0.4
Gain mismatch between Channel 1 and
Channel 2 signal path calculated as
(Gainout1-Gainout0)/
GMIS_SIG_PATH
%
Fixed Gain Mode;
((Gainout1+Gainout0)*0.5)(2)
VCC=5.0V; 4.55%VREG <
VAGC_EN < 95.45%VREG
-40℃≤TA ≤160°C
-0.35
0.55
Input referred offset for IN0 channel(2)
measured with input shorted and exciter
coil connected
VCC=3.3V, 5.0V;
Fixed Gain Mode;
30%VREG < VAGC_EN
95.45%VREG
150
50
170
100
µV
<
Vin_off
Input referred offset for IN1 channel(2)
measured with input shorted and exciter
coil connected
µV
-40℃≤TA ≤160°C
Input referred noise for the complete
signal path for single ended output for
each channel(2)
nSIG_PATH_SE
25
nV/√Hz
nV/√Hz
Input referred noise for the complete
signal path for differential output for each
channel(2)
nSIG_PATH_DIFF
36
Excitation
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Product Folder Links: LDC5072-Q1
English Data Sheet: SNOSD47
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