LA6572
Pin Description
Pin No.
Pin Name
Description
1
MUTE1
MUTE2
CH1 and 2 output ON/OFF
CH3 output ON/OFF
2
3
V
2
Power supply for CH3, 4, and 5. Short-circuited with V 1.
CC
CC
4
V
5-
Output pin (-) for channel 5
Output pin (+) for channel 5
Output pin (+) for channel 4
Output pin (-) for channel 4
Output pin (+) for channel 3
Output pin (-) for channel 3
Output pin (+) for channel 2
Output pin (-) for channel 2
Output pin (+) for channel 1
Output pin (-) for channel 1
O
5
V
5+
4+
4-
O
6
V
O
7
V
V
O
8
3+
O
9
V
V
3-
O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
2+
O
V
V
2-
O
1+
O
V
V
1-
O
1
Power supply for CH1, 2. Short-circuited with V 2.
CC
CC
V
V
1
Input pin for channel 1, input AMP output
Input pin (-) for channel 1
IN
1-
1+
2
IN
V
Input pin (+) for channel 1
IN
V
Input pin for channel 2, input AMP output
Input pin (-) for channel 2
IN
V 2-
IN
V
2+
Input pin (+) for channel 2
IN
V
V
3
Input pin for channel 3, input AMP output
Input pin (-) for channel 3
IN
3-
IN
V
3+
Input pin (+) for channel 1
IN
EN-REG
REG-OUT
3.3V ON/OFF pin that operates with 3.3VREG. EN: H→3.3VREG:ON, EN: L→3.3VREG:OFF
Collector of PNP transistor connected to output 3.3VREG.
PNP transistor base connected
VREF-AMP (CH5 output (TYP: 1.65V))
Reference voltage applied pin
REG-IN
VREF-OUT(CH5)
VREF-IN
V
4+
4-
Input pin (+) for channel 4
IN
V
V
V
Input pin (-) for channel 4
IN
4
Input pin for channel 4, input AMP output
Input pin (+) for channel 5
IN
5+
IN
V
V
5-
Input pin (-) for channel 5
IN
5
Input pin for channel 5, input AMP output
Signal system GND
IN
S-GND
MUTE3
CH4 output ON/OFF
* Center frame (FR) becomes GND for the power system (P-GND). Set this to the minimum potential together with
S-GND.
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