L
SMD Wraparound Ultra Low Value
Thin Film Resistors
Vishay Sfernice
SUGGESTED LAND PATTERN (to IPC-7351A)
Gmin.
Xmax.
Zmax.
DIMENSIONS (in millimeter)
CHIP SIZE
Zmax.
2.37
2.76
3.91
4.66
5.93
Gmin.
0.35
0.74
1.85
2.44
3.71
Xmax.
0.98
1.40
1.73
1.45
2.67
0603
0705/0805
1206
1505
2010
Note
Size 2512 under development
•
Option: Enlarged Terminations
For stringent and special power dissipation requirements,
the thermal resistance between the resistive layer and
the solder joint can be reduced using enlarged terminations
chip resistors which are soldered on large and thick
copper pads acting as heat sinks (see application note:
“Power Dissipation in High Precision Vishay Sfernice Chip
Resistors and Arrays (P Thin Film, PRA Arrays, CHP Thick
Film)”: www.vishay.com/doc?53048).
For enlarged terminations: Please consult Vishay Sfernice.
ELECTRICAL SPECIFICATIONS
POWER DERATING CURVE
Resistance range:
Resistance tolerance:
Power dissipation:
0.1 Ω to 9.99 Ω
1 % to 10 %
0.125 mW to 1 W at + 70 °C
100
80
60
40
20
0
Temperature coefficient: Down to 100 ppm/°C
CLIMATIC SPECIFICATIONS
Operating temp. range:
- 55 °C to + 155 °C
MECHANICAL SPECIFICATIONS
Substrate:
Alumina
0
20
40
60 70 80
100
120
140 155
Resistive layer:
Coating:
NiCr + Ta2O5
Silicone
Ambient Temperature in °C
Terminations:
Solderable
TOLERANCE AND TCR VS. OHMIC VALUE
B type: SnPb over nickel barrier
N type: SnAg over nickel barrier
G type: Gold over nickel barrier
TIGHTEST
VALUE
RANGE
BEST TCR
(ppm/°C)
TOLERANCE
(%)
TERMINATIONS
0R1 < 0R25
0R25 < 0R5
0R5 < 9R99
0R1 < 0R5
0R5 < 9R99
1
1
300
200
100
300
200
N or B
N or B
N or B
G
1
10
5
G
www.vishay.com
58
For technical questions, contact: sfer@vishay.com
Document Number: 53018
Revision: 29-Oct-09