Datasheet > KSZ8864CNXI

KSZ8864CNXI

更新时间： 2024-02-22 16:36:56

品牌	Logo	应用领域
美国微芯 - MICROCHIP		局域网（LAN）标准以太网：16GBASE-T 电信电信集成电路
页数	文件大小	规格书
96页	1237K
描述
IC ETHERNET SWITCH 4PORT 64QFN

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技术参数
数据手册

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KSZ8864CNXI 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	HVQCCN, LCC64,.32SQ,16
Reach Compliance Code：	compliant	Factory Lead Time：	17 weeks
风险等级：	2.34	Samacsys Description：	Ethernet ICs 4-Port 10/100 Switch w/ 2x MAC I/F, MII, RMII
其他特性：	SEATED HT-CALCULATED	数据速率：	100000 Mbps
JESD-30 代码：	S-XQCC-N64	JESD-609代码：	e3
长度：	8 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	64
收发器数量：	2	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC64,.32SQ,16
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	座面最大高度：	0.9 mm
标称供电电压：	1.2 V	表面贴装：	YES
电信集成电路类型：	ETHERNET TRANSCEIVER	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.4 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	8 mm
Base Number Matches：	1

KSZ8864CNXI 数据手册

KSZ8864CNX/RMNUB

Integrated 4-Port 10/100 Managed Switch with

Two MACs MII or RMII Interfaces

• Programmable Weighted Fair Queuing for Ratio

Control

Features

Advanced Switch Features

• Re-Mapping of 802.1p Priority Field Per Port

Basis

• IEEE 802.1q VLAN Support for up to 128 VLAN

Groups (Full-Range 4096 of VLAN IDs)

Integrated 4-Port 10/100 Ethernet Switch

• Static MAC Table Supports up to 32 Entries

• VLAN ID Tag/Untagged Options, Per Port Basis

• New Generation Switch with Four MACs and Four

PHYs that are Fully Compliant with the IEEE

802.3u Standard

• IEEE 802.1p/q Tag Insertion or Removal on a Per

Port Basis Based on Ingress Port (Egress)

• Non-Blocking Switch Fabric Ensures Fast Packet

Delivery by Utilizing a 1K MAC Address Lookup

Table and a Store-and-Forward Architecture

• Programmable Rate Limiting at the Ingress and

Egress on a Per Port Basis

• Jitter-Free Per Packet Based Rate Limiting Sup-

port

• On-Chip 64Kbyte Memory for Frame Buffering

(Not Shared with 1K Unicast Address Table)

• Broadcast Storm Protection with Percentage Con-

trol (Global and Per Port Basis)

• Full-Duplex IEEE 802.3x Flow Control (PAUSE)

with Force Mode Option

• IEEE 802.1d Rapid Spanning Tree Protocol RSTP

Support

• Half-Duplex Back Pressure Flow Control

• HP Auto MDI/MDI-X and IEEE Auto Crossover

Support

• LinkMD^®TDR-Based Cable Diagnostics to Iden-

tify Faulty Copper Cabling

• Tail Tag Mode (1 Byte Added Before FCS) Sup-

port at Port 4 to Inform the Processor Which

Ingress Port Receives the Packet

• 1.4 Gbps High-Performance Memory Bandwidth

and Shared Memory Based Switch Fabric with

Fully Non-Blocking Configuration

• MII Interface of MAC Supports Both MAC Mode

and PHY Mode

• Per Port LED Indicators for Link, Activity, and 10/

100 Speed

• Dual MII/RMII with MAC 3 SW3-MII/RMII and

MAC 4 SW4-MII/RMII Interfaces

• Register Port Status Support for Link, Activity,

Full-/Half-Duplex and 10/100 Speed

• Enable/Disable Option for Huge Frame Size up to

2000 Bytes Per Frame

• On-Chip Terminations and Internal Biasing Tech-

nology for Cost Down and Lowest Power Con-

sumption

• IGMP v1/v2 Snooping (IPv4) Support for Multicast

Packet Filtering

• IPv4/IPv6 QoS Support

Switch Monitoring Features

• Support Unknown Unicast/Multicast Address and

Unknown VID Packet Filtering

• Port Mirroring/Monitoring/Sniffing: Ingress and/or

Egress Traffic to Any Port or MII/RMII

• Self-Address Filtering

• MIB Counters for Fully Compliant Statistics Gath-

ering 34 MIB Counters Per Port

Comprehensive Configuration Register Access

• Serial Management Interface (MDC/MDIO) to All

PHYs Registers and SMI Interface (MDC/MDIO)

to All Registers

• High-Speed SPI (up to 25 MHz) and I²C Master

Interface to all Internal Registers

• Loopback Support for MAC, PHY, and Remote

Diagnostic of Failure

• Interrupt for the Link Change on Any Ports

Low-Power Dissipation

• Full-Chip Software Power-Down and Per Port

Software Power-Down

• I/O Pins Strapping and EEPROM to Program

Selective Registers in Unmanaged Switch Mode

• Energy-Detect Mode Support <0.1W Full-Chip

Power Consumption When All Ports Have No

Activity

• Control Registers Configurable on the Fly (Port-

Priority, 802.1p/d/q, AN…)

QoS/CoS Packet Prioritization Support

• Very-Low Full-Chip Power Consumption (~0.3W),

without Extra Power Consumption on Transform-

ers

• Per Port, 802.1p and DiffServ-Based

• 1/2/4-Queue QoS Prioritization Selection

 2016 Microchip Technology Inc.

DS00002229A-page 1

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中文翻译

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与KSZ8864CNXI相关器件

型号	品牌	获取价格	描述	数据表
KSZ8864CNXIA	MICROCHIP	获取价格	Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
KSZ8864CNXIA-TR	MICROCHIP	获取价格	暂无描述
KSZ8864CNXI-TR	MICROCHIP	获取价格	IC SWITCH 4 PORT MII/RMII 64QFN
KSZ8864RMN	MICREL	获取价格	Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
KSZ8864RMNC-TR	MICROCHIP	获取价格	Ethernet Transceiver, QCC64
KSZ8864RMNI	MICREL	获取价格	Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
KSZ8864RMNUB	MICROCHIP	获取价格	DATACOM, ETHERNET TRANSCEIVER, QCC64
KSZ8864RMNUB-TR	MICROCHIP	获取价格	IC ETHERNET SWITCH 4PORT
KSZ8864RMNUB-TR-VAO	MICROCHIP	获取价格	Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
KSZ8864RMNUB-VAO	MICROCHIP	获取价格	Ethernet Transceiver, QCC64

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