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KMC68EN360EM33L PDF预览

KMC68EN360EM33L

更新时间： 2024-01-11 01:38:35
品牌 Logo 应用领域
恩智浦 - NXP 通信时钟局域网数据传输外围集成电路
页数 文件大小 规格书
14页 223K
描述
4 CHANNEL(S), 10Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP240, PLASTIC, QFP-240

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中文翻译

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KMC68EN360EM33L 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, QFP-240
针数：240Reach Compliance Code：not_compliant
ECCN代码：3A991HTS代码：8542.31.00.01
风险等级：5.78地址总线宽度：32
边界扫描：YES总线兼容性：68000
最大时钟频率：33.34 MHz通信协议：ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; BISYNC
数据编码/解码方法：NRZ; NRZI; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER); DIFF BIPH-LEVEL最大数据传输速率：1.25 MBps
外部数据总线宽度：32JESD-30 代码：S-PQFP-G240
JESD-609代码：e0长度：31.305 mm
低功率模式：YES湿度敏感等级：3
串行 I/O 数：4端子数量：240
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：FQFP
封装形状：SQUARE封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：220认证状态：Not Qualified
座面最大高度：4.15 mm最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：YES技术：HCMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：31.305 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：1

KMC68EN360EM33L 数据手册

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Freescale Semiconductor, Inc.  
Order this document  
by MC68360D  
MOTOROLA  
SEMICONDUCTOR  
PRODUCT INFORMATION  
MC68360  
Product Brief  
MC68360 QUad Integrated Communication  
Controller (QUICC™)  
INTRODUCTION  
The MC68360 QUad Integrated Communication Controller (QUICC™) is a versatile one-chip integrated  
microprocessor and peripheral combination that can be used in a variety of controller applications. It  
particularly excels in communications activities. The QUICC (pronounced “quick”) can be described as a  
next-generation MC68302 with higher performance in all areas of device operation, increased flexibility,  
major extensions in capability, and higher integration. The term "quad" comes from the fact that there are  
four serial communications controllers (SCCs) on the device; however, there are actually seven serial  
channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).  
QUICC Key Features  
The following list summarizes the key MC68360 QUICC features:  
• CPU32+ Processor (4.5 MIPS at 25 MHz)  
— 32-Bit Version of the CPU32 Core (Fully Compatible with the CPU32)  
— Background Debug Mode  
— Byte-Misaligned Addressing  
• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)  
• Up to 32 Address Lines (At Least 28 Always Available)  
• Complete Static Design (0–25-MHz Operation)  
• Slave Mode To Disable CPU32+ (Allows Use with External Processors)  
— Multiple QUICCs Can Share One System Bus (One Master)  
— MC68040 Companion Mode Allows QUICC To Be an MC68040 Companion  
Chip and Intelligent Peripheral (22 MIPS at 25 MHz)  
— Also Supports External MC68030-Type Bus Masters  
— All QUICC Features Usable in Slave Mode  
• Memory Controller (Eight Banks)  
— Contains Complete Dynamic Random-Access Memory (DRAM) Controller  
— Each Bank Can Be a Chip Select or Support a DRAM Bank  
— Up to 15 Wait States  
— Glueless Interface to DRAM Single In-Line Memory Modules (SIMMs), Static Random-Access  
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without  
notice.  
© MOTOROLA 1993  
For More Information On This Product,  
Go to: www.freescale.com  
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