Datasheet > KM684002-25

KM684002-25

更新时间： 2022-12-13 10:25:58

品牌	Logo	应用领域
三星 - SAMSUNG		/
页数	文件大小	规格书
9页	152K
描述
512Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial, Extended and Industrial Temperature Range.

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数据手册

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KM684002-25 数据手册

PRELIMINARY

KM684002, KM684002E, KM684002I

CMOS SRAM

TIMING WAVE FORM OF READ CYCLE(2()WE=VIH)

tRC

ADD

tAA

tHZ(3,4,5)

tCO

tOHZ

tOE

tOLZ

tOH

tLZ(4,5)

Data Valid

Data Out

tPU

tPD

Icc

Vcc

50%

ISB

Current

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or VOL Levels.

4. At any given temperature and voltage condition, t HZ(Max.) is less than tLZ (Min.) both for a given device and from device to device.

§Æ

5. Transition is measured ±200

from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycl e.

TIMING WAVE FORM OF WRITE CYCLE(1()OE=Clock)

tWC

ADD

tWR(5)

tAW

tCW(3)

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data Valid

Data In

tOHZ(6)

High-Z(8)

Data Out

- 6 -

Rev 3.0

June -1997

1...3 4 567 8 9

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