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KM416S1021CT-G7 PDF预览

KM416S1021CT-G7

更新时间: 2024-01-17 01:21:52
品牌 Logo 应用领域
三星 - SAMSUNG 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
8页 82K
描述
512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface

KM416S1021CT-G7 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP50,.46,32
针数:50Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.73Is Samacsys:N
访问模式:DUAL BANK PAGE BURST最长访问时间:5.5 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):143 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G50JESD-609代码:e0
长度:20.95 mm内存密度:16777216 bit
内存集成电路类型:SYNCHRONOUS DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:50字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP50,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.002 A子类别:DRAMs
最大压摆率:0.15 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10.16 mmBase Number Matches:1

KM416S1021CT-G7 数据手册

 浏览型号KM416S1021CT-G7的Datasheet PDF文件第2页浏览型号KM416S1021CT-G7的Datasheet PDF文件第3页浏览型号KM416S1021CT-G7的Datasheet PDF文件第4页浏览型号KM416S1021CT-G7的Datasheet PDF文件第5页浏览型号KM416S1021CT-G7的Datasheet PDF文件第6页浏览型号KM416S1021CT-G7的Datasheet PDF文件第7页 
Preliminary  
KM416S1021C  
CMOS SDRAM  
512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• SSTL_3 (Class II) compatible with multiplexed address  
• Dual banks operation  
The KM416S1021C is 16,777,216 bits synchronous high data  
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,  
fabricated with SAMSUNG¢s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock I/O transactions are possible on every clock  
cycle. Range of operating frequencies, programmable burst  
length and programmable latencies allow the same device to be  
useful for a variety of high bandwidth, high performance mem-  
ory system applications.  
• MRS cycle with address key programs  
- CAS latency (2 & 3)  
- Burst length (1, 2, 4, 8 & Full page)  
- Burst type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part No.  
Max Freq.  
Interface Package  
SSTL_3 54  
• 64ms refresh period (4K cycle)  
KM416S1021CT-G7  
143MHz  
KM416S1021CT-GS 100MHz(CL=2)  
KM416S1021CT-G8 125MHz  
(Class II) TSOP(II)  
* KM416S1021CT-GS : CL=2 only  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
512K x 16  
512K x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
L(U)DQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 1. May '98  

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