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KM416S1021C PDF预览

KM416S1021C

更新时间: 2024-01-04 04:24:40
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器
页数 文件大小 规格书
8页 82K
描述
512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface

KM416S1021C 数据手册

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Preliminary  
KM416S1021C  
CMOS SDRAM  
512K x 16Bit x 2 Banks Synchronous DRAM with SSTL interface  
FEATURES  
GENERAL DESCRIPTION  
• JEDEC standard 3.3V power supply  
• SSTL_3 (Class II) compatible with multiplexed address  
• Dual banks operation  
The KM416S1021C is 16,777,216 bits synchronous high data  
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,  
fabricated with SAMSUNG¢s high performance CMOS technol-  
ogy. Synchronous design allows precise cycle control with the  
use of system clock I/O transactions are possible on every clock  
cycle. Range of operating frequencies, programmable burst  
length and programmable latencies allow the same device to be  
useful for a variety of high bandwidth, high performance mem-  
ory system applications.  
• MRS cycle with address key programs  
- CAS latency (2 & 3)  
- Burst length (1, 2, 4, 8 & Full page)  
- Burst type (Sequential & Interleave)  
• All inputs are sampled at the positive going edge of the system  
clock.  
• Burst read single-bit write operation  
• DQM for masking  
ORDERING INFORMATION  
• Auto & self refresh  
Part No.  
Max Freq.  
Interface Package  
SSTL_3 54  
• 64ms refresh period (4K cycle)  
KM416S1021CT-G7  
143MHz  
KM416S1021CT-GS 100MHz(CL=2)  
KM416S1021CT-G8 125MHz  
(Class II) TSOP(II)  
* KM416S1021CT-GS : CL=2 only  
FUNCTIONAL BLOCK DIAGRAM  
LWE  
Data Input Register  
LDQM  
Bank Select  
512K x 16  
512K x 16  
DQi  
CLK  
ADD  
Column Decoder  
Latency & Burst Length  
LCKE  
Programming Register  
LWCBR  
LRAS  
LCBR  
LWE  
LCAS  
LDQM  
Timing Register  
CLK  
CKE  
CS  
RAS  
CAS  
WE  
L(U)DQM  
Samsung Electronics reserves the right to  
change products or specification without  
notice.  
*
REV. 1. May '98  

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