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KM416C4104CS-5 PDF预览

KM416C4104CS-5

更新时间: 2024-09-28 14:51:51
品牌 Logo 应用领域
三星 - SAMSUNG 动态存储器光电二极管内存集成电路
页数 文件大小 规格书
36页 946K
描述
EDO DRAM, 4MX16, 50ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50

KM416C4104CS-5 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2,
针数:50Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.02
风险等级:5.92访问模式:FAST PAGE WITH EDO
最长访问时间:50 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
JESD-30 代码:R-PDSO-G50长度:20.95 mm
内存密度:67108864 bit内存集成电路类型:EDO DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:50
字数:4194304 words字数代码:4000000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX16
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL宽度:10.16 mm
Base Number Matches:1

KM416C4104CS-5 数据手册

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KM416C4004C,KM416C4104C  
CMOS DRAM  
4M x 16bit CMOS Dynamic RAM with Extended Data Out  
DESCRIPTION  
This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random  
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-5 or -6) are optional features of this family.  
All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 4Mx16 EDO Mode DRAM family  
is fabricated using Samsung¢s advanced CMOS process to realize high band-width, low power consumption and high reliability.  
• Extended Data Out Mode operation  
FEATURES  
• 2 CAS Byte/Word Read/Write operation  
• Part Identification  
• CAS-before-RAS refresh capability  
• RAS-only and Hidden refresh capability  
• Fast parallel test mode capability  
• TTL(5.0V) compatible inputs and outputs  
• Early Write or output enable controlled write  
• JEDEC Standard pinout  
- KM416C4004C(5.0V, 8K Ref.)  
- KM416C4104C(5.0V, 4K Ref.)  
ActivePowerDissipation  
Unit : mW  
4K  
• Available in Plastic TSOP(II) package  
• +5.0V±10% power supply  
Speed  
-5  
8K  
495  
440  
660  
-6  
605  
Refresh Cycles  
Part  
NO.  
Refresh  
cycle  
Refresh time  
FUNCTIONAL BLOCK DIAGRAM  
Normal  
KM416C4004C*  
KM416C4104C  
8K  
4K  
64ms  
RAS  
UCAS  
LCAS  
W
Vcc  
Vss  
Control  
Clocks  
VBB Generator  
* Access mode & RAS only refresh mode  
: 8K cycle/64ms  
Lower  
Data in  
Buffer  
CAS-before-RAS & Hidden refresh mode  
: 4K cycle/64ms  
DQ0  
to  
DQ7  
Row Decoder  
Refresh Timer  
Lower  
Data out  
Buffer  
Refresh Control  
Memory Array  
Performance Range  
OE  
4,194,304 x 16  
Cells  
Refresh Counter  
Row Address Buffer  
Col. Address Buffer  
Upper  
Data in  
Buffer  
Speed  
tRAC  
50ns  
60ns  
tCAC  
13ns  
15ns  
tRC  
tHPC  
20ns  
25ns  
A0~A12  
(A0~A11)*1  
DQ8  
to  
DQ15  
-5  
-6  
84ns  
104ns  
Upper  
Data out  
Buffer  
A0~A8  
(A0~A9)*1  
Column Decoder  
Note) *1 : 4K Refresh  
SAMSUNG ELECTRONICS CO., LTD. reserves the right to  
change products and specifications without notice.  

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