Datasheet > K4H560838D-GLA20

K4H560838D-GLA20

更新时间： 2023-02-15 00:00:00

品牌	Logo	应用领域
三星 - SAMSUNG		动态存储器双倍数据速率
页数	文件大小	规格书
26页	291K
描述
DDR DRAM, 32MX8, 0.75ns, CMOS, PBGA60, FBGA-60

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中文翻译

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数据手册

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K4H560838D-GLA20 数据手册

256Mb

DDR SDRAM

Key Features

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• MRS cycle with address key programs

-. Read latency 2, 2.5 (clock)

-. Burst length (2, 4, 8)

-. Burst type (sequential & interleave)

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)

• Data I/O transactions on both edges of data strobe

• Edge aligned data output, center aligned data input

• LDM,UDM/DM for write masking only

• Auto & Self refresh

• 7.8us refresh interval(8K/64ms refresh)

• Maximum burst refresh cycle : 8

• 60 Ball FBGA package

ORDERING INFORMATION

Part No.

Org.

Max Freq.

Interface

Package

K4H560438D-GC(L)B3

K4H560438D-GC(L)A2

K4H560438D-GC(L)B0

K4H560838D-GC(L)B3

K4H560838D-GC(L)A2

K4H560838D-GC(L)B0

K4H561638D-GC(L)B3

K4H561638D-GC(L)A2

K4H561638D-GC(L)B0

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

B3(DDR333@CL=2.5)

A2(DDR266@CL=2)

B0(DDR266@CL=2.5)

64M x 4

SSTL2

60 ball FBGA

32M x 8

SSTL2

60 ball FBGA

16M x 16

Operating Frequencies

- B3(DDR333)

133MHz

- A2(DDR266A)

- B0(DDR266B)

100MHz

Speed @CL2

133MHz

Speed @CL2.5

166MHz

133MHz

*CL : Cas Latency

Rev. 2.2 Mar. ’03

- 1 -

12 3 4 5 6 7...26

中文翻译

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