Datasheet > K3S7V2000M-TC

K3S7V2000M-TC

更新时间： 2024-02-13 03:16:26

品牌	Logo	应用领域
三星 - SAMSUNG		/
页数	文件大小	规格书
27页	1079K
描述
64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

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K3S7V2000M-TC 数据手册

K3S7V2000M-TC

Synch. MROM

64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM

FEATURES

GENERAL DESCRIPTION

· JEDEC standard 3.3V power supply

· LVTTL compatible with multiplexed address

· Address: Row address: RA0 ~ RA12

Column address: CA0 ~ CA7 (x32): CA0 ~ CA8 (x16)

· Switchable organization

The K3S7V2000M-TC is a synchronous high bandwidth mask

programmable ROM fabricated with SAMSUNG¢s high perfor-

mance CMOS process technology and is organized either as

4,194,304 x16bit(word mode) or as 2,097,152 x32bit(double

word mode) depending on polarity of WORD pin.(see pin func-

tion description). Synchronous design allows precise cycle con-

trol, with the use of system clock, I/O transactions are possible

on every clock cycle. Range of operating frequencies, program-

mable burst length and programmable latencies allow the same

device to be useful for a variety of high bandwidth, high perfor-

mance memory system applications.

4,194,304 x 16(word mode) /

2,097,152 x 32(double word mode)

· All inputs are sampled at the rising edge of the system clock

· Read Performance at memory point of view

@33MHz 4-1-1-1 (RAS Latency=1, CAS Latency=3)

@50MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)

@66MHz 5-1-1-1 (RAS Latency=1, CAS Latency=4)

@83MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)

@100MHz 7-1-1-1 (RAS Latency=2, CAS Latency=5)

· tSAC : 6ns

ORDERING INFORMATION

· Default mode by user requirement

· MRS cycle with address key programs

-. RAS Latency(1 & 2)

Part NO.

MAX Freq.

100MHz

83MHz

Interface

Package

K3S7V2000M-TC10

K3S7V2000M-TC12

K3S7V2000M-TC15

K3S7V2000M-TC20

K3S7V2000M-TC30

-. CAS Latency(3 ~ 6)

-. Burst Length : 4, 8

-. Burst Type : Sequential & Interleaved

LVTTL

86TSOP2

66MHz

· DQM for data-out masking

· Package :86TSOP2 - 400

50MHz

33MHz

FUNCTIONAL BLOCK DIAGRAM

Q16

Q15

Q31

Output

Buffer

4M x 16 /2M x 32

Cell Array

CLK

ADD

Column Decoder

Latency & Burst Length

Programming Register

LCKE

LRAS

CKE

LMR

LCAS

Timing Register

RAS

CLK

CAS

DQM

* Samsung Electronics reserves the right to

change products or specification without notice.

12 3 4 5 6 7...27

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与K3S7V2000M-TC相关器件

型号	品牌	获取价格	描述	数据表
K3S7V2000M-TC10	SAMSUNG	获取价格	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
K3S7V2000M-TC12	SAMSUNG	获取价格	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
K3S7V2000M-TC15	SAMSUNG	获取价格	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
K3S7V2000M-TC20	SAMSUNG	获取价格	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
K3S7V2000M-TC30	SAMSUNG	获取价格	64M-Bit (4Mx16 /2Mx32) Synchronous MASKROM
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