Datasheet > K10P48M50SF0

K10P48M50SF0

更新时间： 2022-11-11 19:19:06

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
59页	1732K
描述
K10 Sub-Family

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K10P48M50SF0 数据手册

Dimensions

7 Dimensions

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to http://www.freescale.com and perform a keyword

search for the drawing’s document number:

If you want the drawing for this package

48-pin LQFP

Then use this document number

98ASH00962A

98ARH99048A

48-pin QFN

8 Pinout

8.1 K10 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

EzPort

LQFP

-QFN

VDD

VSS

PTE16

PTE17

PTE18

PTE19

ADC0_DP0

ADC0_DM0

VDDA

ADC0_SE4a

ADC0_SE5a

ADC0_SE6a

ADC0_SE7a

ADC0_DP0

ADC0_DM0

VDDA

ADC0_SE4a

ADC0_SE5a

ADC0_SE6a

ADC0_SE7a

ADC0_DP0

ADC0_DM0

VDDA

PTE16

SPI0_PCS0

SPI0_SCK

SPI0_SOUT

SPI0_SIN

UART2_TX

UART2_RX

FTM_CLKIN0

FTM_CLKIN1

FTM0_FLT3

PTE17

PTE18

PTE19

LPTMR0_ALT3

UART2_CTS_b I2C0_SDA

UART2_RTS_b I2C0_SCL

VREFH

VREFL

VSSA

VREFH

VREFL

VSSA

VREF_OUT/

CMP1_IN5/

CMP0_IN5

VREF_OUT/

CMP1_IN5/

CMP0_IN5

VREF_OUT/

CMP1_IN5/

CMP0_IN5

K10 Sub-Family Data Sheet, Rev. 4 5/2012.

Freescale Semiconductor, Inc.

1...51 52 535455 56 57...59

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