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K10P100M100SF2 PDF预览

K10P100M100SF2

更新时间： 2024-01-04 15:34:49
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飞思卡尔 - FREESCALE /
页数 文件大小 规格书
63页 1750K
描述
Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz

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K10P100M100SF2 数据手册

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Document Number: K10P100M100SF2  
Rev. 4, 3/2011  
Freescale Semiconductor  
Data Sheet: Product Preview  
K10P100M100SF2  
K10 Sub-Family Data Sheet  
Supports the following:  
MK10N512VLL100  
Features  
Human-machine interface  
– Low-power hardware touch sensor interface (TSI)  
– General-purpose input/output  
•
•
Operating Characteristics  
– Voltage range: 1.71 to 3.6 V  
– Flash write voltage range: 1.71 to 3.6 V  
– Temperature range (ambient): -40 to 105°C  
•
•
•
Analog modules  
– Two 16-bit SAR ADCs  
– Programmable gain amplifier (up to x64) integrated  
into each ADC  
– 12-bit DAC  
– Three analog comparators (CMP) containing a 6-bit  
DAC and programmable reference input  
– Voltage reference  
Performance  
– Up to 100 MHz ARM Cortex-M4 core with DSP  
instructions delivering 1.25 Dhrystone MIPS per  
MHz  
Memories and memory interfaces  
– Up to 512 KB program flash memory on non-  
FlexMemory devices  
Timers  
•
– Up to 128 KB RAM  
– Serial programming interface (EzPort)  
– FlexBus external bus interface  
– Programmable delay block  
– Eight-channel motor control/general purpose/PWM  
timer  
– Two 2-channel quadrature decoder/general purpose  
timers  
– Periodic interrupt timers  
– 16-bit low-power timer  
– Carrier modulator transmitter  
– Real-time clock  
Clocks  
•
•
– 3 to 32 MHz crystal oscillator  
– 32 kHz crystal oscillator  
– Multi-purpose clock generator  
System peripherals  
– 10 low-power modes to provide power optimization  
based on application requirements  
– Memory protection unit with multi-master  
protection  
– 16-channel DMA controller, supporting up to 64  
request sources  
Communication interfaces  
– Two Controller Area Network (CAN) modules  
– Three SPI modules  
– Two I2C modules  
– Five UART modules  
•
– Secure Digital host controller (SDHC)  
– I2S module  
– External watchdog monitor  
– Software watchdog  
– Low-leakage wakeup unit  
Security and integrity modules  
•
– Hardware CRC module to support fast cyclic  
redundancy checks  
– 128-bit unique identification (ID) number per chip  
This document contains information on a product under development. Freescale  
reserves the right to change or discontinue this product without notice.  
© 2010–2011 Freescale Semiconductor, Inc.  
Preliminary  
1234567...63

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