Datasheet > K10P100M100SF2V2

K10P100M100SF2V2

更新时间： 2024-01-13 05:04:27

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		/
页数	文件大小	规格书
69页	1793K
描述
K10 Sub-Family

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数据手册

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K10P100M100SF2V2 数据手册

Document Number: K10P100M100SF2V2

Rev. 1, 6/2012

Freescale Semiconductor

Data Sheet: Advance Information

K10P100M100SF2V2

K10 Sub-Family

Supports the following:

MK10DN512VLL10

Features

Analog modules

– Two 16-bit SAR ADCs

– Programmable gain amplifier (PGA) (up to x64)

integrated into each ADC

– 12-bit DAC

– Two transimpedance amplifiers

– Three analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– Voltage reference

•

Operating Characteristics

– Voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40 to 105°C

•

Performance

– Up to 100 MHz ARM Cortex-M4 core with DSP

instructions delivering 1.25 Dhrystone MIPS per

MHz

Timers

•

Memories and memory interfaces

– Up to 512 KB program flash memory on non-

FlexMemory devices

– Programmable delay block

– Eight-channel motor control/general purpose/PWM

timer

– Two 2-channel quadrature decoder/general purpose

timers

– Periodic interrupt timers

– 16-bit low-power timer

– Carrier modulator transmitter

– Real-time clock

– Up to 128 KB RAM

– Serial programming interface (EzPort)

– FlexBus external bus interface

Clocks

•

– 3 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

Communication interfaces

– Two Controller Area Network (CAN) modules

– Three SPI modules

– Two I2C modules

– Five UART modules

•

System peripherals

– Multiple low-power modes to provide power

optimization based on application requirements

– Memory protection unit with multi-master

protection

– 16-channel DMA controller, supporting up to 63

request sources

– Secure Digital host controller (SDHC)

– I2S module

– External watchdog monitor

– Software watchdog

– Low-leakage wakeup unit

Security and integrity modules

•

– Hardware CRC module to support fast cyclic

redundancy checks

– 128-bit unique identification (ID) number per chip

This document contains information on a new product. Specifications and

information herein are subject to change without notice.

Preliminary

General Business Information

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