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JANKC2N7434

更新时间： 2024-09-30 19:50:23
品牌 Logo 应用领域
英飞凌 - INFINEON /
页数 文件大小 规格书
28页 341K
描述
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET

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JANKC2N7434 技术参数

生命周期：ActiveReach Compliance Code：compliant
风险等级：5.76配置：Single
最大漏极电流 (Abs) (ID)：31 AFET 技术：METAL-OXIDE SEMICONDUCTOR
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
极性/信道类型：N-CHANNEL最大功率耗散 (Abs)：3 W
子类别：FET General Purpose PowerBase Number Matches：1

JANKC2N7434 数据手册

 浏览型号JANKC2N7434的Datasheet PDF文件第2页浏览型号JANKC2N7434的Datasheet PDF文件第3页浏览型号JANKC2N7434的Datasheet PDF文件第4页浏览型号JANKC2N7434的Datasheet PDF文件第5页浏览型号JANKC2N7434的Datasheet PDF文件第6页浏览型号JANKC2N7434的Datasheet PDF文件第7页 
INCH-POUND  
The documentation and process conversion  
measures necessary to comply with this revision  
shall be completed by 1 June 2013.  
MIL-PRF-19500/661D  
17 April 2013  
SUPERSEDING  
MIL-PRF-19500/661C  
7 August 2006  
PERFORMANCE SPECIFICATION SHEET  
SEMICONDUCTOR DEVICE, FIELD EFFECT RADIATION HARDENED  
(TOTAL DOSE AND SINGLE EVENT EFFECTS) TRANSISTORS, N-CHANNEL, SILICON,  
TYPES 2N7444, 2N7434, 2N7391, AND 2N7392,  
JANTXVR AND JANSR  
This specification is approved for use by all Departments  
and Agencies of the Department of Defense.  
The requirements for acquiring the product described herein shall consist of  
this specification sheet and MIL-PRF-19500.  
1. SCOPE  
1.1 Scope. This specification covers the performance requirements for an N-channel, enhancement-mode,  
MOSFET, radiation hardened (total dose and single event effects (SEE)), power transistor intended for use in high  
density power switching applications. Two levels of product assurance are provided for each device type specified in  
MIL-PRF-19500, with avalanche energy maximum rating (EAS) and maximum avalanche current (IAS). See 6.5 for  
JANHC and JANKC die versions.  
1.2 Physical dimensions. See figure 1, TO-254AA.  
1.3 Maximum ratings. Unless otherwise specified, TC = +25°C.  
Type  
PT (1)  
PT  
TA =  
+25°C  
W
VDS  
VDG  
VGS  
ID1  
(3) (4)  
ID2  
(3) (4)  
TC = +100°C  
A dc  
IS  
IDM  
(5)  
TJ  
and  
TSTG  
VISO  
70,000 ft  
altitude  
RθJC  
(2)  
W
V dc  
V dc  
V dc  
A dc  
A dc  
A(pk)  
V dc  
°C/W  
°C  
2N7444  
2N7434  
2N7391  
2N7392  
250  
250  
250  
250  
3.0  
3.0  
3.0  
3.0  
0.5  
0.5  
0.5  
0.5  
200  
250  
400  
500  
200  
250  
400  
500  
35.0  
31.0  
22.0  
18.0  
25.0  
19.0  
14.0  
11.7  
35.0  
31.0  
22.0  
18.0  
140  
124  
88  
-55  
to  
+150  
NA  
250  
400  
500  
±20  
±20  
±20  
±20  
72  
(1) Derate linearly 2.0 W/°C for TC > +25°C.  
(2) See figure 2, thermal impedance curves.  
(3) The following formula derives the maximum theoretical ID limit. ID is limited by package and internal wires  
and may be limited by pin diameter:  
-
TJM TC  
( on ) at  
TJM  
=
ID  
(
)
x
(
)
RθJC  
RDS  
(4) See figure 3, maximum drain current graphs.  
(5) IDM = 4 x ID1 as calculated in note 3.  
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,  
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to Semiconductor@dla.mil. Since  
contact information can change, you may want to verify the currency of this address information using the  
ASSIST Online database at https://assist.dla.mil.  
AMSC N/A  
FSC 5961  
1234567...28

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