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ISL9113ERAZ-EVZ PDF预览

ISL9113ERAZ-EVZ

更新时间: 2024-02-28 05:03:06
品牌 Logo 应用领域
瑞萨 - RENESAS /
页数 文件大小 规格书
15页 1003K
描述
Low Input Voltage and High Efficiency Synchronous Boost Converter with 1.3A Switch

ISL9113ERAZ-EVZ 数据手册

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ISL9113  
Pin Configurations  
FIXED OUTPUT  
(8 LD DFN)  
TOP VIEW  
ADJUSTABLE OUTPUT  
(8 LD DFN)  
TOP VIEW  
1
1
2
SW  
V
SW  
V
8
7
6
8
7
PGND  
PGND  
2
V
V
BAT  
BAT  
OUT  
OUT  
AGND  
EN  
6
5
AGND  
EN  
3
4
3
4
NC  
NC  
FB  
FAULT  
5
FIXED OUTPUT  
(6 BUMP WLCSP)  
TOP VIEW  
ADJUSTABLE OUTPUT  
(6 BUMP WLCSP)  
TOP VIEW  
PGND  
PGND  
A2  
B2  
C2  
A2  
B2  
C2  
A1  
B1  
A1  
B1  
SW  
SW  
V
V
OUT  
V
V
OUT  
BAT  
EN  
BAT  
EN  
C1  
C1  
FAULT  
FB  
Pin Descriptions  
8 LD DFN  
PIN NUMBERS  
6 BUMP WLCSP  
PIN NUMBERS  
SYMBOL  
PIN DESCRIPTIONS  
FIXED  
OUTPUT  
ADJUSTABLE  
OUTPUT  
FIXED  
OUTPUT  
ADJUSTABLE  
OUTPUT  
1
2
3
4
1
2
3
-
A2  
B2  
-
A2  
PGND  
VOUT  
NC  
Power ground  
Device output  
No connection  
B2  
-
-
C2  
FAULT  
Fault output; outputs logic LOW under a number of fault conditions (see  
Table 1 on page 9).  
-
4
5
-
C2  
C1  
FB  
EN  
Feedback pin of the converter. Connect voltage divider resistors between  
VOUT, FB and GND for desired output.  
5
C1  
The EN pin is an active-HIGH logic input for enabling the device. When  
asserted HIGH, the boost function begins. When asserted LOW, the device  
is completely disabled, and current is blocked from flowing from the SW pin  
to the output and vice versa. This pin should be tied either HIGH to enable  
the device, or LOW to disable the device.  
6
7
6
7
-
-
AGND  
VBAT  
Analog ground  
B1  
B1  
Device input supply from a battery. Connect a 4.7µF ceramic capacitor to  
the power ground.  
8
8
A1  
-
A1  
-
SW  
The SW pin is the switching node of the power converter. Connect one  
terminal of the inductor to the SW pin and the other to power input.  
EPAD  
The exposed pad (available only in the 8 Ld DFN package) must be  
connected to PGND pin for proper electrical performance. Place as many  
vias as possible under the pad connecting to the system GND plane for  
optimal thermal performance.  
FN8313 Rev 3.00  
February 23, 2015  
Page 4 of 15  

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