Datasheet > ISL706CEH

ISL706CEH

更新时间： 2023-12-20 18:44:06

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
23页	984K
描述
Rad-Hard, 5.0V/3.3V μ-Processor Supervisory Circuits

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数据手册

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ISL706CEH 数据手册

ISL705xRH, ISL705xEH, ISL706xRH, ISL706xEH, ISL735xEH, ISL736xEH

Pin Descriptions(Continued)

ISL7x5AxH

ISL7x5BxH

ISL7x5CxH

ISL7x6AxH

ISL7x6BxH

ISL7x6CxH

NAME

DESCRIPTION

PFO

Power Fail Output. PFO is an active-low, push-pull output of a threshold detector that

indicates the voltage at the PFI pin is less than V

PFI

WDI

Watchdog Input. WDI is a tri-state input that monitors microprocessor activity. If the

microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated, WDO goes

low. As long as reset is asserted or WDI is tri-stated, the watchdog timer will stay

cleared and will not count. As soon as reset is released and WDI is driven high or low,

the timer will start counting. Floating WDI or connecting WDI to a high impedance

tri-state buffer disables the watchdog feature.

RST

Reset. RST is an active-low, push-pull output that is guaranteed to be low after V

reaches 1.2V. As V rises, RST stays low. When V rises above a 4.65V

DD DD

(ISL7x5AxH/BxH/CxH) or 3.08V (ISL7x6AxH/BxH/CxH) reset threshold, an internal

timer releases RST after about 200ms. RST pulses low whenever V goes below the

reset threshold. If a brownout condition occurs in the middle of a previously initiated

reset pulse, the pulse will continue for at least 140ms. On power-down, after V falls

below the reset threshold, RST goes low and is guaranteed low until V drops below

1.2V.

RST

Reset. RST is an active-high, push-pull output. RST is the inverse of RST.

RST_OD Reset. RST_OD is an active-low, open-drain output that goes low when reset is asserted.

This pin can be pulled up to V with a resistor consistent with the sink and leakage

current specifications of the output. Behavior is otherwise identical to the RST pin.

WDO

Watchdog Output. WDO is an active-low, push-pull output that goes low if the

microprocessor does not toggle WDI within 1.6s and WDI is not tri-stated. WDO is

usually connected to the non-maskable interrupt input of a microprocessor. When V

drops below the reset threshold, WDO will go low whether or not the watchdog timer

has timed out. Reset is simultaneously asserted, thus preventing an interrupt. Since

floating WDI disables the internal timer, WDO goes low only when V drops below the

reset threshold, thus functioning as a low line output.

Timing Diagrams

RST

1.2V

RST

WDI

FIGURE 4. RST, RST, MR TIMING DIAGRAM

FN7662 Rev.6.01

Mar 2, 2022

Page 6 of 22

1...3 4 567 8 9...23

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