ISL2671286
Typical Connection Diagram
+5V SUPPLY
VREF
+
+
0.1
F
10 F
VREF
+VCC
DCLOCK
DOUT
REFP-P
+IN
–IN
P/ C
GND
CS/SHDN
SERIAL
INTERFACE
Pin Configuration
Pin Descriptions
ISL2671286
PIN
(8 LD SOIC)
TOP VIEW
PIN NAME
VREF
+IN
NUMBER
DESCRIPTION
Reference input
1
2
3
Non-inverting input
VREF
+IN
1
2
3
4
8
7
6
5
+VCC
–IN
Inverting input. Connect to ground or remote
sense point.
DCLOCK
DOUT
GND
4
5
Ground
CS/SHDN
Chip select when low; shut-down mode when
high.
–IN
DOUT
6
Serial output data word comprises 12 bits of
data. In operation, data is valid on falling
edge of DCLOCK. Second clock pulse after
falling edge of CS/SHDN enables serial
output. After one null bit, data is valid for
next 12 edges.
GND
CS/SHDN
DCLOCK
+VCC
7
8
Data clock synchronizes serial data transfer.
Power supply
Ordering Information
PART NUMBER
(Notes 1, 2)
+VCC RANGE
(V)
TEMP RANGE
(°C)
PKG.
PART MARKING
2671286 IBZ
2671286 IPZ
PACKAGE
8 Ld SOIC
8 Ld PDIP
DWG. #
M8.15
E8.3
ISL2671286IBZ (Note 3)
4.50 to 5.25
4.50 to 5.25
-40°C to +85°C
-40°C to +85°C
Coming Soon
ISL2671286IPZ
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL2671286. For more information on MSL please see Tech Brief TB363.
FN7863.0
November 1, 2011
2