Datasheet > ISD4004-16MSY

ISD4004-16MSY

更新时间： 2024-02-19 10:16:42

品牌	Logo	应用领域
新唐 - NUVOTON		光电二极管商用集成电路
页数	文件大小	规格书
36页	931K
描述
SINGLE-CHIP, MULTIPLE-MESSAGES VOICE RECORD/PLAYBACK DEVICES 8-, 10-, 12-, AND 16-MINUTE DURATION

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技术参数
数据手册

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ISD4004-16MSY 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	SOP, SOP28,.4	针数：	28
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.06	商用集成电路类型：	SPEECH SYNTHESIZER WITH RCDG
JESD-30 代码：	R-PDSO-G28	长度：	17.93 mm
功能数量：	1	端子数量：	28
片上内存类型：	FLASH	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP28,.4
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
电源：	3 V	认证状态：	Not Qualified
最长读取时间：	960 s	座面最大高度：	2.64 mm
子类别：	Audio Synthesizer ICs	最大压摆率：	40 mA
最大供电电压 (Vsup)：	3.3 V	最小供电电压 (Vsup)：	2.7 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.52 mm	Base Number Matches：	1

ISD4004-16MSY 数据手册

ISD4004 SERIES

PIN NAME

FUNCTION

SOIC /

PDIP

XCLK

External Clock Input: The ISD4004 series is configured at

the factory with an internal sampling clock frequency

centered to 1 percent of specification. The frequency is

then maintained to a variation of 2.25 percent over the

entire commercial temperature and operating voltage

ranges. The internal clock has a –6/+4 percent tolerance

over the industrial temperature and voltage ranges. A

regulated power supply is recommended for industrial

temperature range parts. If greater precision is required, the

device can be clocked through the XCLK pin as follows:

Part Number

ISD4004-08M

ISD4004-10M

ISD4004-12M

ISD4004-16M

Sample Rate

8.0 kHz

Required Clock

1024 kHz

6.4 kHz

819.2 kHz

682.7 kHz

512 kHz

5.3 kHz

4.0 kHz

These recommended clock rates should not be varied

because the anti-aliasing and smoothing filters are fixed.

Otherwise, aliasing problems can occur if the sample rate

differs from the one recommended. The duty cycle on the

input clock is not critical, as the clock is immediately divided

by two. If the XCLK is not used, this input must be

connected to ground.

SCLK

Serial Clock: This is the input clock to the ISD4004 device.

It is generated by the master device (typically

microcontoller) and is used to synchronize the data transfer

in and out of the device through the MOSI and MISO lines,

respectively. Data is latched into the ISD4004 on the rising

edge of SCLK and shifted out of the device on the falling

edge of SCLK.

Publication Release Date: March 2017

- 10 -

Revision 1.32

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