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ISD2590T PDF预览

ISD2590T

更新时间: 2024-01-31 03:52:53
品牌 Logo 应用领域
华邦 - WINBOND 可编程只读存储器电动程控只读存储器电可擦编程只读存储器按钮和信息提示光电二极管商用集成电路
页数 文件大小 规格书
42页 372K
描述
Consumer IC

ISD2590T 技术参数

生命周期:Obsolete包装说明:,
Reach Compliance Code:unknown风险等级:5.83
Is Samacsys:NBase Number Matches:1

ISD2590T 数据手册

 浏览型号ISD2590T的Datasheet PDF文件第6页浏览型号ISD2590T的Datasheet PDF文件第7页浏览型号ISD2590T的Datasheet PDF文件第8页浏览型号ISD2590T的Datasheet PDF文件第10页浏览型号ISD2590T的Datasheet PDF文件第11页浏览型号ISD2590T的Datasheet PDF文件第12页 
ISD2560/75/90/120  
PIN NO.  
PIN NAME  
FUNCTION  
SOIC/ TSOP  
PDIP  
XCLK  
26  
5
External Clock: The external clock input has an internal pull-down  
device. The device is configured at the factory with an internal  
sampling clock frequency centered to ±1 percent of specification.  
The frequency is then maintained to a variation of ±2.25 percent  
over the entire commercial temperature and operating voltage  
ranges. If greater precision is required, the device can be clocked  
through the XCLK pin as follows:  
Part Number  
Sample Rate  
Required Clock  
ISD2560  
8.0 kHz  
1024 kHz  
ISD2575  
6.4 kHz  
819.2 kHz  
682.7 kHz  
512 kHz  
ISD2590  
5.3 kHz  
ISD25120  
4.0 kHz  
These recommended clock rates should not be varied because the  
antialiasing and smoothing filters are fixed, and aliasing problems  
can occur if the sample rate differs from the one recommended.  
The duty cycle on the input clock is not critical, as the clock is  
immediately divided by two. If the XCLK is not used, this input  
must be connected to ground.  
27  
6
P/R  
Playback/Record: The P/R input pin is latched by the falling edge  
of the CE pin. A HIGH level selects a playback cycle while a LOW  
level selects a record cycle. For a record cycle, the address pins  
provide the starting address and recording continues until PD or  
CE is pulled HIGH or an overflow is detected (i.e. the chip is full).  
When a record cycle is terminated by pulling PD or CE HIGH,  
then End-Of-Message ( EOM ) marker is stored at the current  
address in memory. For a playback cycle, the address inputs  
provide the starting address and the device will play until an EOM  
marker is encountered. The device can continue to pass an EOM  
marker if CE is held LOW in address mode, or in an Operational  
Mode. (See Operational Modes section)  
Publication Release Date: May 2003  
- 9 -  
Revision 1.0  

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