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IS93C66A-2GRLI PDF预览

IS93C66A-2GRLI

更新时间： 2024-02-15 20:59:46
品牌 Logo 应用领域
美国芯成 - ISSI 可编程只读存储器
页数 文件大小 规格书
16页 131K
描述
2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM

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中文翻译

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IS93C66A-2GRLI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP8,.25针数：8
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.91
备用内存宽度：8最大时钟频率 (fCLK)：1 MHz
数据保留时间-最小值：40耐久性：1000000 Write/Erase Cycles
JESD-30 代码：R-PDSO-G8JESD-609代码：e0
长度：4.4 mm内存密度：4096 bit
内存集成电路类型：EEPROM内存宽度：16
湿度敏感等级：1功能数量：1
端子数量：8字数：256 words
字数代码：256工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256X16封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
并行/串行：SERIAL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/5 V认证状态：Not Qualified
座面最大高度：1.2 mm串行总线类型：MICROWIRE
最大待机电流：0.000001 A子类别：EEPROMs
最大压摆率：0.003 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.8 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3 mm最长写入周期时间 (tWC)：10 ms
写保护：SOFTWAREBase Number Matches：1

IS93C66A-2GRLI 数据手册

 浏览型号IS93C66A-2GRLI的Datasheet PDF文件第1页浏览型号IS93C66A-2GRLI的Datasheet PDF文件第2页浏览型号IS93C66A-2GRLI的Datasheet PDF文件第4页浏览型号IS93C66A-2GRLI的Datasheet PDF文件第5页浏览型号IS93C66A-2GRLI的Datasheet PDF文件第6页浏览型号IS93C66A-2GRLI的Datasheet PDF文件第7页 
®
IS93C56A  
IS93C66A  
ISSI  
Write Enable (WEN)  
Write All (WRALL)  
The write enable (WEN) instruction must be executed  
before any device programming (WRITE, WRALL,  
ERASE, and ERAL) can be done. When Vcc is applied,  
this device powers up in the write disabled state. The  
devicethenremainsinawritedisabledstateuntilaWEN  
instruction is executed. Thereafter, the device remains  
enabled until a WDS instruction is executed or until Vcc  
is removed. (See Figure 4.) (Note: Chip select must  
remain LOW until Vcc reaches its operational value.)  
The write all (WRALL) instruction programs all registers  
withthedatapatternspecifiedintheinstruction.Aswiththe  
WRITE instruction, the falling edge of CS must occur to  
initiate the self-timed programming cycle. If CS is then  
broughtHIGHafteraminimumwaitof200ns(tCS),theDOUT  
pin indicates the READY/BUSY status of the chip (see  
Figure 6). Vcc is required to be above 4.5V for WRALL to  
function properly.  
Write Disable (WDS)  
Write (WRITE)  
The write disable (WDS) instruction disables all programming  
capabilities. This protects the entire device against acci-  
dental modification of data until a WEN instruction is  
executed. (When Vcc is applied, this part powers up in the  
write disabled state.) To protect data, a WDS instruction  
should be executed upon completion of each programming  
operation.  
TheWRITEinstructionincludes8or16bitsofdatatobe  
written into the specified register. After the last data bit  
has been applied to DIN, and before the next rising edge  
of SK, CS must be brought LOW. If the device is write-  
enabled, then the falling edge of CS initiates the self-  
timed programming cycle (see WEN).  
IfCSisbroughtHIGH,afteraminimumwaitof200ns(5V  
operation) after the falling edge of CS (tCS) DOUT will  
indicatetheREADY/BUSYstatusofthechip.Logical“0”  
meansprogrammingisstillinprogress;logical“1”means  
the selected register has been written, and the part is  
readyforanotherinstruction(seeFigure5).TheREADY/  
BUSYstatuswillnotbeavailableif:a)TheCSinputgoes  
HIGHaftertheendoftheself-timedprogrammingcycle,  
tWP; or b) Simultaneously CS is HIGH, Din is HIGH, and  
SK goes HIGH, which clears the status flag.  
Erase Register (ERASE)  
After the erase instruction is entered, CS must be brought  
LOW.ThefallingedgeofCSinitiatestheself-timedinternal  
programming cycle. Bringing CS HIGH after a minimum of  
tCS, will cause DOUT to indicate the READ/BUSY status of the  
chip:alogical“0”indicatesprogrammingisstillinprogress;  
a logical “1” indicates the erase cycle is complete and the  
part is ready for another instruction (see Figure 8).  
Erase All (ERAL)  
Fullchiperaseisprovidedforeaseofprogramming.Erasing  
the entire chip involves setting all bits in the entire memory  
array to a logical “1” (see Figure 9). Vcc is required to be  
above 4.5V for ERALL to function properly.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
3
Rev. A  
05/02/06  
1234567...16

中文翻译

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IS93C66A-2GRLI 替代型号

型号 品牌 替代类型 描述 数据表
IS93C66A-2GRI ISSI

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 2K-BIT/4K-BIT SERIAL ELECTRICALLY ERASABLE PROM

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