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IS93C56A-3PA PDF预览

IS93C56A-3PA

更新时间: 2024-01-08 12:31:41
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
13页 66K
描述
EEPROM

IS93C56A-3PA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP8,.25针数:8
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.51风险等级:5.91
Is Samacsys:N备用内存宽度:8
最大时钟频率 (fCLK):2 MHz数据保留时间-最小值:40
耐久性:1000000 Write/Erase CyclesJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.4 mm
内存密度:2048 bit内存集成电路类型:EEPROM
内存宽度:16湿度敏感等级:1
功能数量:1端子数量:8
字数:128 words字数代码:128
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128X16
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行:SERIAL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/5 V
认证状态:Not Qualified座面最大高度:1.2 mm
串行总线类型:MICROWIRE最大待机电流:0.000002 A
子类别:EEPROMs最大压摆率:0.001 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
最长写入周期时间 (tWC):5 ms写保护:SOFTWARE
Base Number Matches:1

IS93C56A-3PA 数据手册

 浏览型号IS93C56A-3PA的Datasheet PDF文件第1页浏览型号IS93C56A-3PA的Datasheet PDF文件第2页浏览型号IS93C56A-3PA的Datasheet PDF文件第4页浏览型号IS93C56A-3PA的Datasheet PDF文件第5页浏览型号IS93C56A-3PA的Datasheet PDF文件第6页浏览型号IS93C56A-3PA的Datasheet PDF文件第7页 
®
IS93C46A  
IS93C56A  
IS93C66A  
ISSI  
Write Enable (WEN)  
Write All (WRALL)  
The write enable (WEN) instruction must be executed  
before any device programming (WRITE, WRALL,  
ERASE, and ERAL) can be done. When Vcc is applied,  
this device powers up in the write disabled state. The  
devicethenremainsinawritedisabledstateuntilaWEN  
instruction is executed. Thereafter, the device remains  
enabled until a WDS instruction is executed or until Vcc  
is removed. (See Figure 4.) (Note: Chip select must  
remain LOW until Vcc reaches its operational value.)  
The write all (WRALL) instruction programs all registers  
with the data pattern specified in the instruction. As with  
the WRITE instruction, the falling edge of CS must occur  
to initiate the self-timed programming cycle. If CS is then  
brought HIGH after a minimum wait of 250 ns (tCS), the  
DOUT pinindicatestheREADY/BUSYstatusofthechip(see  
Figure6).  
Write Disable (WDS)  
The write disable (WDS) instruction disables all programming  
capabilities. This protects the entire device against acci-  
dental modification of data until a WEN instruction is  
executed. (When Vcc is applied, this part powers up in the  
write disabled state.) To protect data, a WDS instruction  
should be executed upon completion of each programming  
operation.  
Write (WRITE)  
TheWRITEinstructionincludes8or16bitsofdatatobe  
written into the specified register. After the last data bit  
has been applied to DIN, and before the next rising edge  
of SK, CS must be brought LOW. The falling edge of CS  
initiates the self-timed programming cycle.  
If CS is brought HIGH, after a minimum wait of 250 ns  
(5V operation) after the falling edge of CS (tCS) DOUT will  
indicate the READY/BUSY status of the chip. Logical  
“0” means programming is still in progress, logical “1”  
means the selected register has been written, and the  
part is ready for another instruction (see Figure 5).  
(NOTE: The combination of CS HIGH, DIN HIGH and  
the rising edge of the SK clock, resets the READY/  
BUSY flag. Therefore, to access the READY/BUSY  
flag, this combination of control signals should be  
avoided.) Before a WRITE instruction can be executed,  
the device must be write enabled (see WEN).  
Erase Register (ERASE)  
After the erase instruction is entered, CS must be brought  
LOW.ThefallingedgeofCSinitiatestheself-timedinternal  
programming cycle. Bringing CS HIGH after a minimum of  
tCS, will cause DOUT to indicate the READ/BUSY status of the  
chip:alogical0indicatesprogrammingisstillinprogress;  
a logical “1” indicates the erase cycle is complete and the  
part is ready for another instruction (see Figure 8).  
Erase All (ERAL)  
Fullchiperaseisprovidedforeaseofprogramming.Erasing  
the entire chip involves setting all bits in the entire memory  
array to a logical “1” (see Figure 9).  
INSTRUCTION SET - IS93C46A  
8-bitOrganization  
16-bitOrganization  
(ORG = GND)  
(ORG = Vcc)  
(1)  
(1)  
Instruction  
READ  
Start Bit  
OP Code  
10  
Address  
Input Data  
Address  
Input Data  
1
1
1
(A6-A0)  
11xxxxx  
(A6-A0)  
01xxxxx  
00xxxxx  
(A6-A0)  
10xxxxx  
(A5-A0)  
11xxxx  
(A5-A0)  
01xxxx  
00xxxx  
(A5-A0)  
10xxxx  
WEN (Write Enable)  
WRITE  
00  
(3)  
(2)  
01  
(D7-D0)  
(D15-D0)  
(3)  
(2)  
WRALL (Write All Registers)  
WDS (Write Disable)  
ERASE  
1
1
1
1
00  
(D7-D0)  
(D15-D0)  
00  
11  
ERAL (Erase All Registers)  
00  
Notes:  
1. x = Don't care bit.  
2. If input data is not 16 bits exactly, the last 16 bits will be taken as input data.  
3. If input data is not 8 bits exactly, the last 8 bits will be taken as input data.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
Rev. A  
3
11/12/02  

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