Datasheet > IS61VVF409618B-7.5TQ

IS61VVF409618B-7.5TQ

更新时间： 2024-02-23 23:47:24

品牌	Logo	应用领域
美国芯成 - ISSI		/
页数	文件大小	规格书
34页	1684K
描述
2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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IS61VVF409618B-7.5TQ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	LQFP,
Reach Compliance Code：	compliant	Factory Lead Time：	10 weeks
风险等级：	5.8	最长访问时间：	7.5 ns
其他特性：	FLOW-THROUGH	JESD-30 代码：	R-PQFP-G100
长度：	20 mm	内存密度：	75497472 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	18
功能数量：	1	端子数量：	100
字数：	4194304 words	字数代码：	4000000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	1.89 V
最小供电电压 (Vsup)：	1.71 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

IS61VVF409618B-7.5TQ 数据手册

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IS61LF204836B, IS61VF/VVF204836B

IS61LF409618B, IS61VF/VVF409618B

2M x 36, 4M x 18

72 Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

ADVANCED INFORMATION

OCTOBER 2012

DESCRIPTION

FEATURES

The 72Mb product family features high-speed, low-power

synchronous static RAMs designed to provide burstable,

high-performance memory for communication and network-

ing applications. The IS61LF/VF204836B is organized as

2,096,952 words by 36 bits. The IS61LF/VF409618B is

organized as 4,193,904 words by 18 bits. Fabricated with

ISSI's advanced CMOS technology, the device integrates

a 2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

•

Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

Writecyclesareinternallyself-timedandareinitiatedbythe

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be writ-

ten. Byte write operation is performed by using byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

LF: Vdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)

VF: Vdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)

VVF: Vdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the ADV (burst address

advance) input pin.

• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-

pin PBGA packages

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

ﬂoating.

• Lead-free available

FAST ACCESS TIME

Symbol

Parameter

-6.5

6.5

-7.5

7.5

8.5

117

Units

tkq

Clock Access Time

Cycle Time

tkc

7.5

Frequency

133

MHz

liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device speciﬁcation before relying on

any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause

failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written

assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

Rev. 00B

10/15/2012

12 3 4 5 6 7...34

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与IS61VVF409618B-7.5TQ相关器件

型号	品牌	描述	获取价格	数据表
IS61VVF409618B-7.5TQL	ISSI	2M x 36, 4M x 18 72 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM	获取价格
IS61VVF409618B-7.5TQL-TR	ISSI	IC SRAM 72MBIT 7.5NS 100TQFP	获取价格
IS61VVPS102418B	ISSI	Internal self-timed write cycle	获取价格
IS61VVPS102436B-166TQLI	ISSI	Cache SRAM, 1MX36, 3.8ns, CMOS, PQFP100, LQFP-100	获取价格
IS61VVPS102436B-200B3LI	ISSI	Cache SRAM, 1MX36, 3.1ns, CMOS, PBGA165, TFBGA-165	获取价格
IS61VVPS102436B-200TQLI	ISSI	Cache SRAM, 1MX36, 3.1ns, CMOS, PQFP100, LQFP-100	获取价格

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