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IS61LV3216-20KI PDF预览

IS61LV3216-20KI

更新时间: 2024-01-21 08:15:39
品牌 Logo 应用领域
矽成 - ICSI 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 429K
描述
Standard SRAM, 32KX16, 20ns, CMOS, PDSO44,

IS61LV3216-20KI 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOJ, SOJ44,.44Reach Compliance Code:unknown
风险等级:5.86最长访问时间:20 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-J44
JESD-609代码:e0内存密度:524288 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
端子数量:44字数:32768 words
字数代码:32000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装等效代码:SOJ44,.44封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.01 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.18 mA
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

IS61LV3216-20KI 数据手册

 浏览型号IS61LV3216-20KI的Datasheet PDF文件第2页浏览型号IS61LV3216-20KI的Datasheet PDF文件第3页浏览型号IS61LV3216-20KI的Datasheet PDF文件第4页浏览型号IS61LV3216-20KI的Datasheet PDF文件第5页浏览型号IS61LV3216-20KI的Datasheet PDF文件第7页浏览型号IS61LV3216-20KI的Datasheet PDF文件第8页 
IS61LV3216  
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)  
-10  
Min.  
10  
-12  
Min.  
12  
10  
10  
-15  
Min.  
15  
11  
11  
-20  
Min.  
20  
12  
12  
Symbol Parameter  
Max.  
Max.  
Max.  
Max.  
Unit  
ns  
tWC  
tSCE  
tAW  
Write Cycle Time  
CE to Write End  
9
ns  
Address Setup Time  
to Write End  
9
ns  
tHA  
Address Hold from Write End  
Address Setup Time  
0
0
5
0
0
6
0
0
7
0
0
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSA  
tPWB  
tPWE  
tSD  
LB, UB Valid to End of Write  
WE Pulse Width  
9
10  
8
11  
10  
7
12  
11  
0
7
Data Setup to Write End  
Data Hold from Write End  
WE LOW to High-Z Output  
WE HIGH to Low-Z Output  
5
6
tHD  
0
0
0
8
(2)  
tHZWE  
1
1
1
1
(2)  
tLZWE  
Notes:  
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V  
and output loading specified in Figure 1a.  
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.  
3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to  
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the  
rising or falling edge of the signal that terminates the write.  
6
Integrated Circuit Solution Inc.  
SR009-0B  

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