Datasheet > IS41C44004-50T

IS41C44004-50T

更新时间： 2024-01-05 07:15:29

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
19页	159K
描述
x4 EDO Page Mode DRAM

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技术参数
数据手册

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IS41C44004-50T 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2-24
针数：	24	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.92	访问模式：	FAST PAGE WITH EDO
最长访问时间：	50 ns	其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e0	长度：	17.14 mm
内存密度：	16777216 bit	内存集成电路类型：	EDO DRAM
内存宽度：	4	功能数量：	1
端口数量：	1	端子数量：	24
字数：	4194304 words	字数代码：	4000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP24/26,.36
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	刷新周期：	4096
座面最大高度：	1.2 mm	自我刷新：	NO
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.12 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7.62 mm

IS41C44004-50T 数据手册

IS41C4400X

IS41LV4400X SERIES

ISSI

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the t^REFrefresh requirement is exceeded.

2. V^IH(MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and

V^IL(or between VIL and VIH) and assume to be 1 ns for all inputs.

3. In addition to meeting the transition rate specification, all input signals must transit between V^IHand VIL (or between VIL and VIH) in a

monotonicmanner.

4. If CAS and RAS = V^IH, data output is High-Z.

5. If CAS = V^IL, data output may contain data from the last valid READ cycle.

6. Measured with a load equivalent to one TTL gate and 50 pF.

7. Assumesthatt^RCD- tRCD (MAX). IftRCD isgreaterthanthemaximumrecommendedvalueshowninthistable, tRAC willincreasebythe

amount that t^RCDexceeds the value shown.

8. Assumes that t^RCD• tRCD (MAX).

9. IfCAS isLOWatthefallingedgeofRAS, dataoutwillbemaintainedfromthepreviouscycle. Toinitiateanewcycleandclearthedata

output buffer, CAS and RAS must be pulsed for t^CP.

10. Operation with the t^RCD(MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is

greater than the specified t^RCD(MAX) limit, access time is controlled exclusively by tCAC.

11. Operation within the t^RAD(MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is

greater than the specified t^RAD(MAX) limit, access time is controlled exclusively by tAA.

12. Either t^RCHor tRRH must be satisfied for a READ cycle.

13. t^OFF(MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.

14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS

(MIN),thecycleisanEARLYWRITEcycleandthedataoutputwillremainopencircuitthroughouttheentirecycle.IftRWD •tRWD (MIN),

t^AWD•tAWD (MIN)andtCWD •tCWD (MIN), thecycleisaREAD-WRITEcycleandthedataoutputwillcontaindatareadfromtheselected

cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is

indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.

15. Output parameter (I/O) is referenced to corresponding CAS input.

16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE

WRITE or READ-MODIFY-WRITE is not possible.

17. Write command is defined as WE going low.

18. LATEWRITEandREAD-MODIFY-WRITEcyclesmusthavebotht^ODandtOEH met(OE HIGHduringWRITEcycle)inordertoensure

thattheoutputbufferswillbeopenduringtheWRITEcycle. TheI/OswillprovidethepreviouslywrittendataifCAS remainsLOWand

OE is taken back to LOW after t^OEHis met.

19. The I/Os are in open during READ cycles once tOD or tOFF occur.

20. Determined by falling edge of CAS.

21. Determined by rising edge of CAS.

22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-

MODIFY-WRITE cycles.

23. CAS must meet minimum pulse width.

24. The 3 ns minimum is a parameter guaranteed by design.

25. Enables on-chip refresh and address counters.

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. C

09/29/00

1...5 6 789 10 11...19

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与IS41C44004-50T相关器件

型号	品牌	描述	获取价格	数据表
IS41C44004-50TI	ETC	x4 EDO Page Mode DRAM	获取价格
IS41C44004-60J	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44004-60JI	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IS41C44004-60T	ISSI	EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, TSOP2-24	获取价格
IS41C44004-60TI	ISSI	EDO DRAM, 4MX4, 60ns, CMOS, PDSO24, TSOP2-24	获取价格
IS41C4400X	ISSI	4M x 4 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格

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