IP2003A PDF预览

IP2003A

更新时间: 2025-09-12 03:44:15
品牌 Logo 应用领域
英飞凌 - INFINEON 驱动器半导体电源电路
页数 文件大小 规格书
10页 356K
描述
Synchronous Buck Multiphase Optimized LGA Power Block Integrated Power Semiconductors, Drivers & Passives

IP2003A 数据手册

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PD-96987A  
iP2003A  
Synchronous Buck  
Multiphase Optimized LGA Power Block  
Integrated Power Semiconductors, Drivers & Passives  
Features:  
• Full function multiphase building block  
• Output current 40A continuous with no derating up to  
PCB = 100°C and TCASE = 100°C  
T
• Operating frequency up to 1.0 MHz  
• Proprietary packaging enables ultra low Rth  
• Efficient dual sided cooling  
j-case top  
• Small footprint low profile (9mm x11mm x 2.2mm) package  
• Optimized for very low power losses  
• LGA interface  
iP2003A Power Block  
• Ease of design  
Description  
The iP2003A is a fully optimized solution for high current synchronous buck multiphase applications.  
Board space and design time are greatly reduced because most of the components required for each  
phase of a typical discrete-based multiphase circuit are integrated into a single 9mm x 11mm x 2.2mm  
power block. The only additional components required for a complete multiphase converter are a PWM  
controller, the output inductors, and the input and output capacitors.  
iPOWIR technology offers designers an innovative board space saving solution for applications  
requiring high power densities. iPOWIR technology eases design for applications where component integration  
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for  
layout, heat transfer and component selection.  
Pin # Pin Name  
Pin Function  
1
2
3
VDD  
Supply voltage for the internal circuitry.  
When set to logic level high, internal circuitry  
of the device is enabled. When set to logic  
level low, the PRDY pin is forced low, the  
Control and Sychronous switches are turned  
off, and the supply current reduces to 10µ A.  
ENABLE  
PWM  
iP2003A Internal Block Diagram  
VSWS1  
VSWS2  
TTL-level input signal to MOSFET drivers.  
Power Ready - This pin indicates the status of  
ENABLE or VDD. This output will be driven  
low when ENABLE is logic low or when VDD  
is less than 4.4V (typ.). When ENABLE is  
logic high and VDD is greater than 4.4V (typ.),  
this output is driven high. This output has a  
10mA source and 1mA sink capability.  
VIN  
PRDY  
4
PRDY  
ENABLE  
MOSFET  
Driver with  
dead time  
control  
PWM  
VDD  
VSW  
Power Ground - connection to the ground of  
bulk and filter capacitors.  
Switching Node - connection to the output  
5, 7  
6
PGND  
VSW  
inductor.  
Input voltage pin. External bypass ceramic  
capacitors must be added directly next to the  
block.  
PGND  
8
VIN  
Floating pin. For internal use. Externally, short  
to VSWS2 pin only.  
9
VSWS1  
VSWS2  
Floating pin. For internal use. Externally, short  
to VSWS1 pin only.  
10  
www.irf.com  
1
10/19/05  

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