Datasheet > INT202TFI1

INT202TFI1

更新时间： 2024-02-27 13:24:09

品牌	Logo	应用领域
帕沃英蒂格盛 - POWERINT		驱动器
页数	文件大小	规格书
12页	92K
描述
Low-side Drive and High-side Control for Simultaneous Conduction

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技术参数
数据手册

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INT202TFI1 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	8
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.84
高边驱动器：	NO	输入特性：	SCHMITT TRIGGER
接口集成电路类型：	BUFFER OR INVERTER BASED MOSFET DRIVER	JESD-30 代码：	R-PDSO-G8
功能数量：	1	端子数量：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	TOTEM-POLE	标称输出峰值电流：	0.3 A
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
最大压摆率：	3 mA	最大供电电压：	16 V
最小供电电压：	10 V	标称供电电压：	15 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子位置：	DUAL
断开时间：	1 µs	接通时间：	1 µs
Base Number Matches：	1

INT202TFI1 数据手册

INT202

General Circuit Operation

The three-phase switched reluctance

motor drive circuit shown in Figure 4

illustrates a typical application for the

INT202/201. The LS IN signal directly

controlsMOSFETQ1. TheHS INsignal

causes the INT202 to command the

INT201toturnMOSFETQ2onoroffas

required.

The length of time that the high-side can

remain on is limited by the size of the

bootstrap capacitor. Applications with

extremely long high-side on times

require special techniques discussed in

AN-10.

voltage switching, gate charge, and bias

power. Figure 5 indicates the maximum

switching frequency as a function of

inputvoltageandgatecharge. Forhigher

ambient temperatures, the switching

frequency should be derated linearly.

Maximum frequency of operation is

limitedbypowerdissipationduetohigh-

Local bypassing for the low-side driver

isprovidedbyC1. Bootstrapbiasforthe

high-side driver is provided by D1 and

C2. Slew rate and effects of parasitic

oscillations in the load waveforms are

controlled by resistors R1 and R2.

400

PDIP

SOIC

= 200 V

= 300 V

= 400 V

= 200 V

= 300 V

= 400 V

300

200

100

300

200

100

Theinputsaredesignedtobecompatible

with 5 V CMOS logic levels and should

notbeconnectedtoV_DD. NormalCMOS

power supply sequencing should be

observed. Theorderofsignalapplication

should be V_DD, logic signals, and then

HV+. V_DDshould be supplied from a

low impedance voltage source.

100

Gate Charge (nC)

200

100

Gate Charge (nC)

200

Figure 5. Switching Frequency versus Gate Charge for a) PDIP and b) SOIC.

2/96

1 2 345 6 7...12

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