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IM8R-67025V-35 PDF预览

IM8R-67025V-35

更新时间: 2024-01-25 23:52:49
品牌 Logo 应用领域
TEMIC 静态存储器内存集成电路
页数 文件大小 规格书
23页 257K
描述
Dual-Port SRAM, 8KX16, 35ns, CMOS, CPGA84, PGA-84

IM8R-67025V-35 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:PGA-84Reach Compliance Code:unknown
风险等级:5.45最长访问时间:35 ns
I/O 类型:COMMONJESD-30 代码:S-CPGA-P84
JESD-609代码:e0内存密度:131072 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:16
功能数量:1端口数量:2
端子数量:84字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:8KX16输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA84M,11X11封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified最大待机电流:0.0002 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.3 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

IM8R-67025V-35 数据手册

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MATRA MHS  
M 67025  
The semaphore must use a WRITE/READ sequence in Semaphore initialization is not automatic and must  
order to ensure that no system level conflict will occur. A therefore be incorporated in the power up initialization  
processor requests access to shared resources by procedures. Since any semaphore flag containing a zero  
attempting to write a zero to a semaphore location. If the must be reset to one, initialization should write a one to  
semaphore is already in use, the semaphore request latch all request flags from both sides to ensure that they will  
will contain a zero, yet the semaphore flag will appear as be available when required.  
a one, and the processor will detect this status in the  
subsequent read (see table 5). For example, assume a  
Using Semaphores - Some Examples  
processor writes a zero to the left port at a free semaphore  
location. On a subsequent read, the processor will verify  
that it has written successfully to that location and will  
assume control over the resource concerned. If a  
processor on the right side then attempts to write a zero  
to the same semaphore flag it will fail, as will be verified  
by a subsequent read returning a one from the semaphore  
location on the right side has a READ/WRITE sequence  
been used instead, system conflict problems could have  
occurred during the interval between the read and write  
cycles.  
Perhaps the simplest application of semaphores is their  
use as resource markers for the M 67025’s dual-port  
RAM. If it is necessary to split the 8 k × 16 RAM into two  
4 K × 16 blocks which are to be dedicated to serving either  
the left or right port at any one time. Semaphore 0 can be  
used to indicate which side is controlling the lower  
segment of memory and semaphore 1 can be defined as  
indicating the upper segment of memory.  
To take control of a resource, in this case the lower 4 k of  
It must be noted that a failed semaphore request needs to a dual-port RAM, the left port processor would then write  
be followed by either repeated reads or by writing a one a zero into semaphore flag 0 and then read it back. If  
to the same location. The simple logic diagram for the successful in taking the token (reading back a zero rather  
semaphore flag in figure 2 illusrates the reason for this than a one), the left processor could then take control of  
quite clearly. Two semaphore request latches feed into a the lower 4 k of RAM. If the right processor attempts to  
semaphore flag. The first latch to send a zero to the perform the same function to take control of the resource  
semaphore flag will force its side of the semaphore flag after the left processor has already done so, it will read  
low and other side high. This status will be maintained back a one in response to the attempted write of a zero into  
until a one is written to the same semaphore request latch. semaphore 0. At this point the software may choose to  
Sould a zero be written to the other side’s semaphore attempt to gain control of the second 4 k segment of RAM  
request latch in the meantime, the semaphore flag will flip by writing and then reading a zero in semaphore 1. If  
over to this second side as soon as a one is written to the successful, it will lock out the left processor.  
first side’s request latch. The second side’s flag will now  
Once the left side has completed its task it will write a one  
stay low until its semaphore request latch is changed to a  
to semaphore 0 and may then attempt to access  
one. Thus, clearly, if a semaphore flag is requested and the  
semaphore 1. If semaphore 1 is still occupied by the right  
processor requesting it no longer requires access to the  
side, the left side may abandon its semaphore request and  
resource, the entire system can hang up until a one is  
perform other operations until it is able to write and then  
written to the semaphore request latch concerned.  
read a zero in semaphore 1. If the right processor  
Semaphore timing becomes critical when both sides  
request the same token by attempting to write a zero to it  
at the same time. Semaphore logic is specially conceived  
to resolve this problem. The logic ensures that only one  
side will receive the token if simultaneous requests are  
made. The first side to make a request will receive the  
token where request do not arrive at the same time. Where  
they do arrive at the same time, the logic will assign the  
token arbitrarily to one of the ports. It should be noted,  
however, that semaphores alone do not guarantee that  
access to a resource is secure. As with any powerful  
programming technique, errors can be introduced if  
performs the same operation with semaphore 0, this  
protocol would then allow the two processes to swap 4 k  
blocks of dual-port RAM between one another.  
The blocks do not have to be any particular size, and may  
even be of variable size depending on the complexity of  
the software using the semaphore flags. All eight  
semaphores could be used to divide the dual-port RAM or  
other shared resources into eight parts. Semaphores can  
even be assigned different meanings on each side, rather  
than having a common meaning as is described in the  
above example.  
semaphores are misused or misinterpreted. Code integrity Semaphores are a useful form of arbitration in systems  
is of the utmost performance when semaphores are being such as disk interfaces where the CPU must be locked out  
used instead of slower, more restrictive hardware-intensive of a segment of memory during a data transfer operation,  
systems.  
and the I/0 device cannot tolerate any wait states. If  
Rev. D (29/09/95)  
7

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