IDT79RV4640/IDT79RC64V474
PCI MEZZANINE CARD
PRELIMINARY
IDT7M9510
IDT7M9514
FEATURES:
• PCI Mezzanine Card (PMC) (IEEE 1386) form factor
• 7M9510 High performance IDT79RV4640 MIPS Processor
– 100Mhz, 150Mhz, 180Mhz, 200MHz CPU speeds supported
–
PCI
– host to PCI bridge
– PCI to main memory bridge
– fully compatible to PCI rev 2.1
– high performance PCI interfaces via 96 bytes of posted write
and read prefetch buffers
–
–
50MHz maximum CPU bus frequency
33MHz maximum PCI bus frequency
• 7M9514 High performance IDT79RC64V474 MIPS Processor
– 180Mhz, 200Mhz, 250Mhz CPU speeds supported
• Other Features
–
–
50MHz maximum CPU bus frequency
33MHz maximum PCI bus frequency
–
–
–
–
Manual Cold Reset (Pushbutton and two pin header)
hardware based masking of interrupts
Configurable Timer Interrupt Generator
32 Bits of user defined I/O mapped through system FPGA
• DRAM
–
–
–
72-positionSIMMslot
4MB to 128MB of DRAM supported
32-bitwidth
–
VxWorks Board Support Package available from IDT
DESCRIPTION:
• Flash
The IDT7M9510/7M9514 is a Single Board Computer utilizing IDT's
79RV4640/79RC64V474 MIPS processor. This CPU Mezzanine Card is
designed for use in applications where low profile, parallel board to board
mounting is required. The 7M9510/7M9514 consists of an IDT79RV4640 /
IDT79RC64V474 processor based subsystem that can either form the core
CPU function for an embedded application, or can be an optional add-in
accelerator to a PCI based system through a PCI v2.1 compatible, PMC
Standard(IEEE P1386.1)connector.
Thecardconforms,inlengthandwidthtothestandardsinglesizePMCform
factorasspecifiedinIEEEP1386.1,anditcontainsallthefeaturesrequiredof
atypicalCPUsubsystemforembeddedprocessorapplications. Someofthese
features include: DRAM,Flash,serialports andfullPCIinterruptsupport.
–
–
2MB of on board Flash memory
32-bitwidth
• EPROM
–
–
–
up to 512KB
8-bit width
32 Pin PLCC socket
• Two serial interface ports (16550A compatible)
• Uses Galileo GT-64011 PCI System controller
–
DMA
– fourindependentchannels
– chainingvialinkedlistsofrecords
– byte alignmentonsource anddestination
– transfers through a 32 byte internal FIFO
whichmoves data betweenPCI, memoryanddevices
FUNCTIONAL BLOCK DIAGRAM
Device Bus
PMC User I/O Header
EPROM
8
32
Watch Dog
Timer
Flash
32
IDT
RV4640/
RC64V474
Serial
connector
SIO
System
FPGA
Serial
connector
DRAM
32
33Mhz
GT-64011
PCI Bus
32
4095 drw 01
March 1999
1
1999 Integrated Device Technology, Inc.