IDT77V550
Pin Definitions
Pin Number
Symbol
SCLK
Type
Input
Description
1
40 MHz system clock.
Reset input. Active low.
4
RESETI
RESETO
RESETO
RESETP0
RESETP1
RESETP2
RESETP3
RESETP4
RESETP5
RESETP6
RESETP7
SWAD0
SWAD1
SWAD2
SWAD3
SWAD4
SWAD5
SWAD6
SWAD7
MD/C
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
I/O
68
69
5
Reset output. Active low.
Reset output. Active high.
Reset output to port number 0. Active low.
Reset output to port number 1. Active low.
Reset output to port number 2. Active low.
Reset output to port number 3. Active low.
Reset output to port number 4. Active low.
Reset output to port number 5. Active low.
Reset output to port number 6. Active low.
Reset output to port number 7. Active low.
Switch VCI address. LSB.
6
7
8
10
11
12
13
45
46
47
48
50
51
52
53
41
42
43
31
32
33
34
36
37
38
39
15
16
17
18
19
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address.
Switch VCI address. MSB.
Control bus. Selector for accessing data or control word.
Control bus. Selector for read or write operation.
Control bus. Master strobe. Latching on positive edge.
Control bus. Data bus to Switch Controller. LSB.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller.
Control bus. Data bus to Switch Controller. MSB.
DPI to Switch Manager interface. Data bus.
DPI to Switch Manager interface. Data bus.
DPI to Switch Manager interface. Data bus.
DPI to Switch Manager interface. Data bus.
Linecard to Switch Manager DPI interface. New frame.
MR/W
MSTRB
MDATA0
MDATA1
MDATA2
MDATA3
MDATA4
MDATA5
MDATA6
MDATA7
IPD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
Input
Input
Input
Input
IPD1
IPD2
IPD3
IFRM
Table 1 Pin Descriptions (Part 1 of 2)
4 of 19
June 22, 2001