Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> IDT77V1254L25L25PG

IDT77V1254L25L25PG

更新时间： 2024-01-02 16:44:28

品牌	Logo	应用领域
艾迪悌 - IDT		ATM集成电路 SONET集成电路 SDH集成电路电信电路异步传输模式
页数	文件大小	规格书
47页	808K
描述
Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

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技术参数
数据手册

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IDT77V1254L25L25PG 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
Reach Compliance Code：	unknown	风险等级：	5.92
Is Samacsys：	N	JESD-30 代码：	S-PQFP-G144
JESD-609代码：	e0	端子数量：	144
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP144,1.2SQ	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	ATM/SONET/SDH ICs
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.635 mm	端子位置：	QUAD
Base Number Matches：	1

IDT77V1254L25L25PG 数据手册

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IDT77V1254L25

Transmission Description

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Refer to Figure 4. Cell transmission begins with the PHY-ATM Inter-

face. An ATM layer device transfers a cell into the 77V1254L25 across

the Utopia or DPI transmit bus. This cell enters a 3-cell deep transmit

FIFO. Once a complete cell is in the FIFO, transmission begins by

passing the cell, four bits (MSB first) at a time to the 'Scrambler'.

The 'Scrambler' takes each nibble of data and exclusive-ORs them

against the 4 high order bits (X(t), X(t-1), X(t-2), X(t-3)) of a 10 bit

pseudo-random nibble generator (PRNG). Its function is to provide the

appropriate frequency distribution for the signal across the line.

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The PRNG is clocked every time a nibble is processed, regardless of

whether the processed nibble is part of a data or command byte. Note

however that only data nibbles are scrambled. The entire command byte

(X _C) is NOT scrambled before it's encoded (see diagram for illustra-

tion). The PRNG is based upon the following polynomial:

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This encode/decode implementation has several very desirable prop-

erties. Among them is the fact that the output data bits can be repre-

sented by a set of relatively simple symbols;

X + X + 1

Run length is limited to <= 5;

With this polynomial, the four output data bits (D3, D2, D1, D0) will be

Disparity never exceeds +/- 1.

generated from the following equations:

On the receiver, the decoder determines from the received symbols

whether a timing marker command (X_8) or a start-of-cell command was

sent (X_X or X_4). If a start-of-cell command is detected, the next 53

bytes received are decoded and forwarded to the descrambler. (See TC

Receive Block Diagram, Figure 5).

D3 = d3 xor X(t-3)

D2 = d2 xor X(t-2)

D1 = d1 xor X(t-1)

D0 = d0 xor X(t)

The following nibble is scrambled with X(t+4), X(t+3), X(t+2), and

X(t+1).

A scrambler lock between the transmitter and receiver occurs each

time an X_X command is sent. An X_X command is initiated only at the

beginning of a cell transfer after the PRNG has cycled through all of its

states (2 - 1 = 1023 states). The first valid ATM data cell transmitted

after power on will also be accompanied with an X_X command byte.

Each time an X_X command byte is sent, the first nibble after the last

escape (X) nibble is XOR'd with 1111b (PRNG = 3FFx).

Because a timing marker command (X_8) may occur at any time, the

possibility of a reset PRNG start-of-cell command and a timing marker

command occurring consecutively does exist (e.g. X_X_X_8). In this

case, the detection of the last two consecutive escape (X) nibbles will

cause the PRNG to reset to its initial 3FFx state. Therefore, the PRNG is

clocked only after the first nibble of the second consecutive escape pair.

Once the data nibbles have been scrambled using the PRNG, the

nibbles are further encoded using a 4b/5b process. The 4b/5b scheme

ensures that an appropriate number of signal transitions occur on the

line. A total of seventeen 5-bit symbols are used to represent the sixteen

4-bit data nibbles and the one escape (X) nibble. The table below lists

the 4-bit data with their corresponding 5-bit symbols:

3 of 47

September 21, 2001

1 234 5 6 7...47

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与IDT77V1254L25L25PG相关器件

型号	品牌	描述	获取价格	数据表
IDT77V1254L25L25PGI	IDT	Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks	获取价格
IDT77V1254L25PG	ETC	ATM Processor	获取价格
IDT77V1254L25PG8	IDT	ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144	获取价格
IDT77V1254L25PGI	ETC	ATM Processor	获取价格
IDT77V1254L25PGI8	IDT	ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144	获取价格
IDT77V1254L25PGI9	IDT	ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144	获取价格

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