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IDT77V1254L25L25PG PDF预览

IDT77V1254L25L25PG

更新时间: 2024-02-02 01:16:44
品牌 Logo 应用领域
艾迪悌 - IDT ATM集成电路SONET集成电路SDH集成电路电信电路异步传输模式
页数 文件大小 规格书
47页 808K
描述
Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

IDT77V1254L25L25PG 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
Is Samacsys:NJESD-30 代码:S-PQFP-G144
JESD-609代码:e0端子数量:144
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP144,1.2SQ封装形状:SQUARE
封装形式:FLATPACK电源:3.3 V
认证状态:Not Qualified子类别:ATM/SONET/SDH ICs
标称供电电压:3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.635 mm端子位置:QUAD
Base Number Matches:1

IDT77V1254L25L25PG 数据手册

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Ordering Information  
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Revision History  
3/2/98:  
ADVANCE INFORMATION. Initial Draft.  
PRELIMINARY. TXOSC pin name changed to OSC. Missing information added. Package code corrected in ordering code.  
10/5/98  
11/30/98  
PRELIMINARY. Numerous minor edits. Corrections to Figures 26 and 30. Elimination of Line Rate Selection bit in the Master Control  
Registers. IDD1 and IDD2 values updated. Addition of VPI/VCI Swap feature. Improvements to Utopia bus timing parameters.  
3/23/99:  
3/8/01  
Update to new format, revisions to Utopia 1 text.  
Changed from Preliminary to Final. Various typographic corrections. Corrected default values for UTOPIA 2 Port Address in the  
Enhanced Control 1 Registers. Added IDD values for 51 Mbps.Removed Trd minimum spec. IDD Values for 25 Mbps and 51 Mbps  
updated.  
9/21/2001  
Changed values in the Max. column for IDD1 and IDD2 in the DC Electrical Characteristics (All pins except TX and RX) table.  
Changed value in Max. column for t23 in Utopia Level 2 Bus Timing Parameters table. Added Loop Timing Feature section.  
CORPORATE HEADQUARTERS  
2975 Stender Way  
for SALES:  
for Tech Support:  
800-345-7015 or 408-727-6116  
fax: 408-330-1748  
www.idt.com  
email: phyhelp@idt.com  
phone: 408-330-1752  
Santa Clara, CA 95054  
47 of 47  
September 21, 2001  

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