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IDT77V1253L25PGI PDF预览

IDT77V1253L25PGI

更新时间： 2024-01-27 15:14:58
品牌 Logo 应用领域
艾迪悌 - IDT ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
44页 449K
描述
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS

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IDT77V1253L25PGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP144,1.2SQ
针数：144Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.29
应用程序：ATMJESD-30 代码：S-PQFP-G144
JESD-609代码：e0长度：28 mm
功能数量：1端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP144,1.2SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：4.07 mm子类别：ATM/SONET/SDH ICs
最大压摆率：0.14 mA标称供电电压：3.3 V
表面贴装：YES技术：CMOS
电信集成电路类型：ATM/SONET/SDH NETWORK INTERFACE温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

IDT77V1253L25PGI 数据手册

 浏览型号IDT77V1253L25PGI的Datasheet PDF文件第2页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第3页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第4页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第6页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第7页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第8页 
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6  
AND 51.2 MBPS ATM NETWORKS  
IDT77V1253  
TABLE 1 — SIGNAL DESCRIPTIONS (CONTINUED):  
SIGNAL NAME  
TXCLK  
PIN NUMBER  
I/O  
In  
SIGNAL DESCRIPTION  
43  
Utopia Transmit Clock. This is a free running clock input.  
TXDATA[15:0]  
32, 31, 30, 29, 28,  
27, 26, 25, 24, 23, 22,  
21, 20, 19, 18, 17  
In  
Utopia 2 Transmit Data. An ATM device transfers cells across this bus to  
the 77V1253 for transmission. Also see TXPARITY.  
34  
Utopia 2 Transmit Enable. Driven by an ATM device to indicate it is  
transmitting data across the TXDATA bus.  
TXEN  
In  
In  
TXPARITY  
33  
Utopia 2 Transmit Data Parity. Odd parity across TXDATA[15:0]. Parity is  
checked and errors are indicated in the Interrupt Status Registers, as  
enabled in the Master Control Registers. No other action is taken in the  
event of an error. Tie high or low if unused.  
TXSOC  
35  
In  
Utopia 2 Transmit Start of Cell. Asserted coincident with the first word of  
data for each cell on TXDATA.  
8-BIT UTOPIA LEVEL 1 SIGNALS (MODE[1:0] = 01)  
SIGNAL NAME  
PIN NUMBER  
I/O  
SIGNAL DESCRIPTION  
RXCLAV[2:0]  
65, 66, 54  
Out  
Utopia 1 Receive Cell Available. Indicates the cell available status of the  
respective port. It is asserted when a full cell is available for retrieval  
from the receive FIFO.  
RXCLK  
46  
In  
Utopia 1 Receive Clock. This is a free running clock input.  
Utopia 1 Receive Data. When one of the three ports is selected, the  
77V1253 transfers received cells to an ATM device across this bus. Bit 5  
in the Diagnostic Control Registers determines whether RXDATA tri-states  
when RXEN[2:0] are high. Also see RXPARITY.  
RXDATA[7:0]  
69, 70, 71, 72,  
73, 74, 75, 76  
Out  
49, 48, 47  
In  
Utopia 1 Receive Enable. Driven by an ATM device to indicate its ability  
to receive data across the RXDATA bus. One for each port.  
RXEN[2:0]  
RXPARITY  
RXSOC  
58  
55  
Out  
Out  
Utopia 1 Receive Data Parity. Odd parity over RXDATA[7:0].  
Utopia 1 Receive Start of Cell. Asserted coincident with the first word of  
data for each cell on RXDATA. Tri-statable as determined by bit 5 in the  
Diagnostic Control Registers.  
TXCLAV[2:0]  
40, 41, 42  
43  
Out  
Utopia 1 Transmit cell Available. Indicates the availability of room in the  
transmit FIFO of the respective port for a full cell.  
TXCLK  
In  
In  
Utopia 1 Transmit Clock. This is a free running clock input.  
TXDATA[7:0]  
24, 23, 22, 21,  
20, 19, 18, 17  
Utopia 1 Transmit Data. An ATM device transfers cells across the bus to  
the 77V1253 for transmission. Also see TXPARITY.  
26, 25, 34  
In  
In  
Utopia 1 Transmit Enable. Driven by an ATM device to indicate it is  
transmitting data across the TXDATA bus. One for each port.  
TXEN[2:0]  
TXPARITY  
33  
Utopia 1 Transmit Data Parity. Odd parity across TXDATA[7:0]. Parity is  
checked and errors are indicated in the Interrupt Status Registers, as  
enabled in the Master Control Registers. No other action is taken in the  
event of an error. Tie high or low if unused.  
TXSOC  
35  
In  
Utopia 1 Transmit Start of Cell. Asserted coincident with the first word of  
data for each cell on TXDATA.  
DPI MODE SIGNALS (MODE[1:0] = 10)  
I/O  
SIGNAL NAME  
PIN NUMBER  
SIGNAL DESCRIPTION  
DPICLK  
43  
In  
DPI Source Clock for Transmit. This is the free-running clock used as the  
source to geenrate Pn_TCLK.  
Pn_RCLK  
51, 49, 48  
In  
DPI Port 'n' Receive Clock. Pn_RCLK is cycled to indicate that the  
interfacing device is ready to receive a nibble of data on Pn_RD[3:0] of  
port 'n'.  
Pn_RD[3:0]  
63, 64, 65, 66,  
69, 70, 71, 72,  
73, 74, 75, 76  
Out  
DPI Port 'n' Receive Data. Cells received on port 'n' are passed to the  
interfacing device across this bus. Each port has its own dedicated bus.  
4781 tbl 03  
5
12345678...44

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