5秒后页面跳转
捷配首页

Datasheet > 电信电路 > ATM/SONET/SDH 集成电路> IDT77V1253L25PGI
IDT77V1253L25PGI PDF预览

IDT77V1253L25PGI

更新时间： 2024-02-06 18:17:52
品牌 Logo 应用领域
艾迪悌 - IDT ATM集成电路SONET集成电路SDH集成电路电信集成电路电信电路异步传输模式
页数 文件大小 规格书
44页 449K
描述
TRIPLE PORT PHY (PHYSICAL LAYER) FOR 25.6 AND 51.2 MBPS ATM NETWORKS

阅读下载

获取价格

IDT77V1253L25PGI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：QFP, QFP144,1.2SQ
针数：144Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.29
应用程序：ATMJESD-30 代码：S-PQFP-G144
JESD-609代码：e0长度：28 mm
功能数量：1端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：QFP
封装等效代码：QFP144,1.2SQ封装形状：SQUARE
封装形式：FLATPACK峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：4.07 mm子类别：ATM/SONET/SDH ICs
最大压摆率：0.14 mA标称供电电压：3.3 V
表面贴装：YES技术：CMOS
电信集成电路类型：ATM/SONET/SDH NETWORK INTERFACE温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：28 mm
Base Number Matches：1

IDT77V1253L25PGI 数据手册

 浏览型号IDT77V1253L25PGI的Datasheet PDF文件第1页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第2页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第4页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第5页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第6页浏览型号IDT77V1253L25PGI的Datasheet PDF文件第7页 
TRIPLEPORTPHY(PHYSICALLAYER)FOR25.6  
AND 51.2 MBPS ATM NETWORKS  
IDT77V1253  
TABLE 1 — SIGNAL DESCRIPTIONS  
LINE SIDE SIGNALS  
SIGNAL NAME  
RX0+,-  
PIN NUMBER  
139, 138  
133, 132  
121, 120  
4, 3  
I/O  
In  
SIGNAL DESCRIPTION  
Port 0 positive and negative receive differential input pair.  
Port 1 positive and negative receive differential input pair.  
Port 2 positive and negative receive differential input pair.  
Port 0 positive and negative transmit differential output pair.  
Port 1 positive and negative transmit differential output pair.  
Port 2 positive and negative transmit differential output pair.  
RX1+,-  
In  
RX2+,-  
In  
TX0+,-  
Out  
Out  
Out  
TX1+,-  
144, 143  
110, 109  
TX2+,-  
UTILITY BUS SIGNALS  
I/O  
SIGNAL NAME  
PIN NUMBER  
SIGNAL DESCRIPTION  
AD[7:0]  
101, 100, 99, 98,  
96, 95, 94, 93  
In/Out  
Utility bus address/data bus. The address input is sampled on the falling  
edge of ALE. Data is output on this bus when a read is performed. Input  
data is sampled at the completion of a write operation.  
ALE  
91  
In  
Utility bus address latch enable. Asynchronous input. An address on the  
AD bus is sampled on the falling edge of ALE. ALE may be either high  
low when the AD bus is being used for data.  
90  
89  
In  
In  
Utility bus asynchronous chip select. CS must be asserted to read or  
CS  
RD  
write an internal register. It may remain asserted at all times if desired.  
Utility bus read enable. Active low asynchronous input. After latching  
an address, a read is performed by deasserting WR and asserting  
RD and CS.  
88  
In  
Utility bus write enable. Active low asynchronous input. After latching  
an address, a write is performed by deasserting RD, placing data  
on the AD bus, and asserting WR and CS. Data is sampled.  
WR  
MISCELLANEOUS SIGNALS  
I/O  
SIGNAL NAME  
PIN NUMBER  
103  
SIGNAL DESCRIPTION  
DA  
In  
Reserved signal. This input must be connected to logic low.  
DNC  
12, 82, 105, 106  
Out  
Do Not Connect. Do not connect these pins to anything external to the  
chip. They must remain open.  
85  
Out  
Interrupt. INT is an open-drain output, driven low to indicate an interrupt.  
Once low, INT remains low until the interrupt status in the appropriate  
interrupt Status Register is read. Interrupt sources are programmable  
via the interrupt Mask Registers.  
INT  
MA  
MB  
114  
115  
6
In  
In  
In  
In  
Reserved signal. This input must be connected to logic low.  
Reserved signal. This input must be connected to logic low.  
Reserved signal. This input must be connected to logic high.  
MM  
MODE[1:0]  
7, 8  
Mode Selects. They determine the configuration of the PHY/ATM  
interface. 00 = UTOPIA Level 2. 01 = UTOPIA Level 1. 10 = DPI.  
11 is reserved.  
OSC  
126  
87  
In  
In  
TTL line rate clock source, driven by a 100 ppm oscillator. 32 MHz  
for 25.6 Mbps; 64 MHz for 51.2 Mbps.  
Reset. Active low asynchronous input resets all control logic, counters  
and FIFOs. A reset must be performed after power up prior to normal  
operation of the part.  
RST  
Receive LED drivers. Driven low for 223 RCLK or DPICLK cycles,  
beginning with RXSOC when that port receives a good (non-null and  
non-errored) cell. Drives 8 mA both high and low. One per port.  
RXLED[2:0]  
81, 80, 79  
Out  
4781 tbl 01  
3
1234567...44

下载PDF

与IDT77V1253L25PGI相关器件

型号 品牌 描述 获取价格 数据表
IDT77V1253L25PGI8 IDT ATM Network Interface, 1-Func, CMOS, PQFP144, 28 X 28 MM, PLASTIC, QFP-144

获取价格
IDT77V1253L25PGI9 IDT ATM Network Interface, 1-Func, CMOS, PQFP144, PLASTIC, QFP-144

获取价格
IDT77V1254L25 IDT Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

获取价格
IDT77V1254L25L25PG IDT Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

获取价格
IDT77V1254L25L25PGI IDT Quad Port PHY (Physical Layer) for 25.6 and 51.2 ATM Networks

获取价格
IDT77V1254L25PG ETC ATM Processor

获取价格

与IDT77V1253L25PGI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证