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IDT73720APQF9 PDF预览

IDT73720APQF9

更新时间: 2024-10-02 14:51:27
品牌 Logo 应用领域
艾迪悌 - IDT 逻辑集成电路
页数 文件大小 规格书
9页 80K
描述
Bus Exchanger, 73 Series, 1-Func, 16-Bit, True Output, CMOS, PQFP80, PLASTIC, QFP-80

IDT73720APQF9 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:QFP,针数:80
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.84Is Samacsys:N
其他特性:BYTE CONTROL ON ALL THREE PORTS系列:73
JESD-30 代码:S-PQFP-G80JESD-609代码:e0
长度:14 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS EXCHANGER位数:16
功能数量:1端口数量:3
端子数量:80最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:QFP封装形状:SQUARE
封装形式:FLATPACK传播延迟(tpd):7 ns
认证状态:Not Qualified座面最大高度:2.45 mm
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
宽度:14 mmBase Number Matches:1

IDT73720APQF9 数据手册

 浏览型号IDT73720APQF9的Datasheet PDF文件第2页浏览型号IDT73720APQF9的Datasheet PDF文件第3页浏览型号IDT73720APQF9的Datasheet PDF文件第4页浏览型号IDT73720APQF9的Datasheet PDF文件第5页浏览型号IDT73720APQF9的Datasheet PDF文件第6页浏览型号IDT73720APQF9的Datasheet PDF文件第7页 
16-BIT TRI-PORT  
BUS EXCHANGER  
IDT73720/A  
FEATURES:  
DESCRIPTION:  
– High-speed16-bitbusexchangeforinterbuscommunicationinthe  
followingenvironments:  
The IDT73720/A Bus Exchanger is a high speed 16-bit bus exchange  
deviceintendedforinter-buscommunicationininterleavedmemorysystems  
and high performance multiplexed address and data buses.  
• Multi-way interleaving memory  
• Multiplexed address and data buses  
– DirectinterfacetoR3051familyRISChipSet™  
• R3051familyofintegratedRISControllerCPUs  
• R3721 DRAM controller  
The Bus Exchanger is responsible for interfacing between the CPU A/  
D bus (CPU address/data bus) and multiple memory data buses.  
The73720/Ausesathreebusarchitecture(X, Y, Z), withcontrolsignals  
suitableforsimpletransferbetweentheCPUbus(X)andeithermemorybus  
(Y or Z). The Bus Exchanger features independent read and write latches  
for each memory bus, thus supporting a variety of memory strategies. All  
three ports support byte enable to independently enable upper and lower  
bytes.  
– Data path for read and write operations  
– Low noise 12mA TTL level outputs  
– Bidirectional 3-bus architecture: X, Y, Z  
• One CPU bus: X  
• Two (interleaved or banked) memory buses:Y & Z  
• Each bus can be independently latched  
– Byte control on all three buses  
– Sourceterminatedoutputsforlownoiseandundershootcontrol  
– 68-pin PLCC and 80-pin PQFP package  
– High-performance CMOS technology.  
FUNCTIONALBLOCKDIAGRAM  
OEYL  
8
Y0:7  
LEXY  
Y-WRITE  
LATCH  
16  
Y8:15  
8
(Even Path)  
8
8
OEYU  
LEYX  
Y-READ  
LATCH  
16  
8
8
16  
OEXL  
OEXU  
PATH  
8
OEXL  
OEYU  
OEYL  
X0:7  
M
U
X
T/R  
BUS CONTROL  
16  
OEU  
OEL  
X8:15  
OEZU  
OEZL  
8
OEXU  
8
16  
8
Z-READ  
LEZX  
LATCH  
16  
OEZL  
8
8
8
Z0:7  
16  
Z-WRITE  
LATCH  
16  
LEXZ  
Z8:15  
8
(Odd Path)  
OEZU  
NOTE:  
1. Logic equations for bus control:  
OEXU = T/R* . OEU*; OEXL = T/R* . OEL*; OEYU = T/R. PATH . OEU*  
OEYL = T/R. PATH . OEL*; OEZU = T/R . PATH* . OEU*; OEZL = T/R . PATH* . OEL*  
COMMERCIAL TEMPERATURE RANGE  
DECEMBER 1999  
1
c
1999 Integrated Device Technology, Inc.  
DSC-2527/7  

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