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IDT72V825L15PF9 PDF预览

IDT72V825L15PF9

更新时间： 2024-01-26 21:00:43
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片
页数 文件大小 规格书
26页 321K
描述
FIFO, 1KX18, 10ns, Synchronous, CMOS, PQFP128, TQFP-128

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IDT72V825L15PF9 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-128针数：128
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.85
Is Samacsys：N最长访问时间：10 ns
周期时间：15 nsJESD-30 代码：R-PQFP-G128
JESD-609代码：e0长度：20 mm
内存密度：18432 bit内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：128字数：1024 words
字数代码：1000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：1KX18可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LFQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：20宽度：14 mm
Base Number Matches：1

IDT72V825L15PF9 数据手册

 浏览型号IDT72V825L15PF9的Datasheet PDF文件第1页浏览型号IDT72V825L15PF9的Datasheet PDF文件第2页浏览型号IDT72V825L15PF9的Datasheet PDF文件第4页浏览型号IDT72V825L15PF9的Datasheet PDF文件第5页浏览型号IDT72V825L15PF9的Datasheet PDF文件第6页浏览型号IDT72V825L15PF9的Datasheet PDF文件第7页 
IDT72V805/72V815/72V825/72V835/72V845  
3.3 V CMOS DUAL SyncFIFO™ 256 x 18, 512 x 18, 1,024 x 18, 4,096 x 18  
COMMERCIAL AND INDUSTRIAL  
TEMPERATURE RANGES  
PIN DESCRIPTION  
Symbol  
Name  
Data Inputs  
I/O  
Description  
DA0–DA17  
I
Data inputs for an 18-bit bus.  
DB0-DB17  
RSA  
Reset  
RSB  
I
I
I
I
I
I
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and  
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.  
WCLKA  
WCLKB  
Write Clock  
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.  
WENA  
WENB  
Write Enable  
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.  
When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.  
RCLKA  
Read Clock  
RCLKB  
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not  
empty.  
RENA  
RENB  
Read Enable  
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN  
is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF is low.  
OEA  
Output Enable  
OEB  
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a  
high-impedance state.  
LDA  
LDB  
Load  
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH  
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the  
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.  
FLA  
FLB  
First Load  
I
I
I
In the single device or width expansion configuration, FL together with WXI and RXI etermine if the mode is IDT  
Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are synchronous  
or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration, FL is grounded on the first  
device (first load device) and set to HIGH for all other devices in the Daisy Chain.  
WXIA  
WXIB  
Write Expansion  
Read Expansion  
In the single device or width expansion configuration, WXI together with FL and RXI Input determine if the mode  
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.  
(See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion  
Out) of the previous device.  
RXIA  
RXIB  
In the single device or width expansion configuration, RXI together with FL and WXI, Input determine if the mode  
is IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.  
(See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read  
Expansion Out) of the previous device.  
FFA/IRA  
FFB/IRB  
Full Flag/  
Input Ready  
O
O
O
O
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full.  
In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to  
the FIFO memory.  
EFA/ORA  
EFB/ORB  
Empty Flag/  
Output Ready  
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is  
empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at  
the outputs.  
PAEA  
PAEB  
Programmable  
Almost-Empty flag  
When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset  
atresetis31fromemptyforIDT72V805LB,63fromemptyforIDT72V815LB,and127fromemptyforIDT7V2825LB/  
72V835LB/72V845LB.  
PAFA  
PAFB  
Programmable  
Almost-Full Flag  
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset  
at reset is 31 from full for IDT72V805LB, 63 from full for IDT72V815LB, and 127 from full for IDT72V825LB/  
72V835LB/72V845LB.  
WXOA/HFA  
WXOB/HFB  
Write Expansion  
In the single device or width expansion configuration, the device is more than half full Out/Half-Full Flag  
when HF is LOW. In the depth expansion configuration, a pulse is sent from WXO to WXI of the next device  
when the last location in the FIFO is written.  
RXOA  
RXOB  
Read Expansion  
Out  
O
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location  
in the FIFO is read.  
QA0–QA17  
QB0-QB17  
Data Outputs  
Data outputs for an 18-bit bus.  
VCC  
Power  
+3.3V power supply pins.  
Ground pins.  
GND  
Ground  
3
1234567...26

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