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IDT54823CTEB PDF预览

IDT54823CTEB

更新时间: 2024-01-27 21:53:26
品牌 Logo 应用领域
艾迪悌 - IDT 驱动逻辑集成电路
页数 文件大小 规格书
9页 182K
描述
Bus Driver, FCT Series, 1-Func, 9-Bit, True Output, CMOS, CDFP24, CERPACK-24

IDT54823CTEB 技术参数

生命周期:Obsolete零件包装代码:DFP
包装说明:DFP,针数:24
Reach Compliance Code:unknown风险等级:5.84
其他特性:WITH CLEAR AND CLOCK ENABLE系列:FCT
JESD-30 代码:R-GDFP-F24JESD-609代码:e0
长度:15.748 mm逻辑集成电路类型:BUS DRIVER
位数:9功能数量:1
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装形状:RECTANGULAR封装形式:FLATPACK
传播延迟(tpd):13.5 ns认证状态:Not Qualified
座面最大高度:2.286 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL宽度:9.144 mm
Base Number Matches:1

IDT54823CTEB 数据手册

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IDT54/74FCT821AT/BT/CT  
HIGH-PERFORMANCE  
CMOS BUS  
INTERFACE REGISTERS  
IDT54/74FCT823AT/BT/CT/DT  
IDT54/74FCT825AT/BT/CT  
Integrated Device Technology, Inc.  
FEATURES:  
• Common features:  
– Low input and output leakage 1µA (max.)  
– CMOS power levels  
– True TTL input and output compatibility  
– VOH = 3.3V (typ.)  
DESCRIPTION:  
The FCT82xT series is built using an advanced dual metal  
CMOS technology. The FCT82xT series bus interface regis-  
ters are designed to eliminate the extra packages required to  
buffer existing registers and provide extra data width for wider  
address/data paths or buses carrying parity. The FCT821T  
are buffered, 10-bit wide versions of the popular FCT374T  
function. The FCT823T are 9-bit wide buffered registers with  
Clock Enable (EN) and Clear (CLR) – ideal for parity bus  
interfacing in high-performance microprogrammed systems.  
TheFCT825Tare8-bitbufferedregisterswithalltheFCT823T  
controls plus multiple enables (OE1, OE2, OE3) to allow multi-  
user control of the interface, e.g., CS, DMA and RD/WR. They  
are ideal for use as an output port requiring high IOL/IOH.  
The FCT82xT high-performance interface family can drive  
large capacitive loads, while providing low-capacitance bus  
loading at both inputs and outputs. All inputs have clamp  
diodes and all outputs are designed for low-capacitance bus  
loading in high-impedance state.  
– VOL = 0.3V (typ.)  
– Meets or exceeds JEDEC standard 18 specifications  
– Product available in Radiation Tolerant and Radiation  
Enhanced versions  
– Military product compliant to MIL-STD-883, Class B  
and DESC listed (dual marked)  
– Available in DIP, SOIC, SSOP, QSOP, CERPACK  
and LCC packages  
• Features for FCT821T/FCT823T/FCT825T:  
– A, B, C and D speed grades  
– High drive outputs (-15mA IOH, 48mA IOL)  
– Power off disable outputs permit “live insertion”  
FUNCTIONAL BLOCK DIAGRAM  
D0  
DN  
EN  
CLR  
CL  
CL  
D
Q
Q
D
Q
Q
CP  
CP  
CP  
OE  
Y
0
YN  
2567 drw 01  
The IDT logo is a registered trademark of Integrated Device Technology, Inc.  
MILITARY AND COMMERCIAL TEMPERATURE RANGES  
AUGUST 1995  
1995 Integrated Device Technology, Inc  
6.21  
DSC-4202/5  
1

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