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IDT2305B-1HDCI8 PDF预览

IDT2305B-1HDCI8

更新时间: 2024-10-03 14:42:43
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
12页 180K
描述
PLL Based Clock Driver, 2305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, SOIC-8

IDT2305B-1HDCI8 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.66
系列:2305输入调节:STANDARD
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
湿度敏感等级:1功能数量:1
反相输出次数:端子数量:8
实输出次数:4最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.25 ns
座面最大高度:1.72 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mm最小 fmax:133 MHz
Base Number Matches:1

IDT2305B-1HDCI8 数据手册

 浏览型号IDT2305B-1HDCI8的Datasheet PDF文件第2页浏览型号IDT2305B-1HDCI8的Datasheet PDF文件第3页浏览型号IDT2305B-1HDCI8的Datasheet PDF文件第4页浏览型号IDT2305B-1HDCI8的Datasheet PDF文件第5页浏览型号IDT2305B-1HDCI8的Datasheet PDF文件第6页浏览型号IDT2305B-1HDCI8的Datasheet PDF文件第7页 
IDT2305B  
3.3V ZERO DELAY  
CLOCK BUFFER  
FEATURES:  
DESCRIPTION:  
• Phase-Lock Loop Clock Distribution  
• 10MHz to 133MHz operating frequency  
• Distributes one clock input to one bank of five outputs  
• Zero Input-Output Delay  
The IDT2305B is a high-speed phase-lock loop (PLL) clock buffer,  
designed to address high-speed clock distribution applications. The zero  
delay is achieved by aligning the phase between the incoming clock and  
the output clock, operable within the range of 10 to 133MHz.  
• Output Skew < 250ps  
The IDT2305B is an 8-pin version of the IDT2309B. IDT2305B accepts  
one reference input, and drives out five low skew clocks. The -1H version  
of this device operates, up to 133MHz frequency and has a higher drive  
thanthe-1device. Allpartshaveon-chipPLLswhichlocktoaninputclock  
on the REF pin. The PLL feedback is on-chip and is obtained from the  
CLKOUTpad.Intheabsenceofaninputclock,theIDT2305Benterspower  
down. In this mode, the device will draw less than 25µA, the outputs are  
tri-stated, and the PLL is not running, resulting in a significant reduction of  
power.  
• Low jitter <175 ps cycle-to-cycle  
• 50ps typical cycle-to-cycle jitter (15pF, 66MHz)  
• IDT2305B-1 for Standard Drive  
• IDT2305B-1H for High Drive  
• No external RC network required  
• Operates at 3.3V VDD  
• Power down mode  
• Available in SOIC and TSSOP packages  
The IDT2305B is characterized for both Industrial and Commercial  
operation.  
NOTE: EOL for non-green parts to occur on 5/13/10 per  
PDNU-09-01  
FUNCTIONALBLOCKDIAGRAM  
8
CLKOUT  
3
CLK1  
PLL  
1
Control  
Logic  
REF  
2
CLK2  
CLK3  
CLK4  
5
7
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
JANUARY 2010  
1
c
2010 Integrated Device Technology, Inc.  
DSC 6994/5  

IDT2305B-1HDCI8 替代型号

型号 品牌 替代类型 描述 数据表
2305B-1HDCGI8 IDT

完全替代

3.3V ZERO DELAY CLOCK BUFFER

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