Datasheet > ICS9248YG-192-T

ICS9248YG-192-T

更新时间： 2024-09-24 22:09:47

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
12页	106K
描述
Frequency Timing Generator for Transmeta Systems

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中文翻译

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数据手册

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ICS9248YG-192-T 数据手册

ICS9248-192

Integrated

Circuit

Systems,Inc.

Frequency Timing Generator for Transmeta Systems

RecommendedApplication:

Transmeta

Pin Configuration

GNDREF

VDDREF

REF

CPU_STOP#

VDDLCPU

GNDLCPU

CPUCLK0

PCI_STOP#

GND_Core

VDD_Core

SEL66/60#

VDD48

GND48

48MHz/CPU3.3v_2.5V#sel

24-48MHz/Sel48_24#

OutputFeatures:

•

1CPU(2.5V or 3.3V selectable) up to 66.6MHz &

overclocking of 66MHz.

PD#

PCICLK0

PCICLK1

PCICLK2

GNDPCI

VDDPCI

PCICLK3

PCICLK4

PCICLK5

SDATA

SCLK

•

6 PCI (3.3V) @ 33.3MHz (all are free running

selectable).

•

1 REF (3.3V) at 14.318MHz.

1 48MHz (3.3V).

1 24_48MHz selectable output.

Features:

•

Supports Spread Spectrum modulation for CPU and

PCI clocks, default -0.4 downspread.

Efficient Power management scheme through stop

clocks and power down modes.

Uses external 14.318MHz crystal, no external load

cap required for CL=18pF crystal.

28-Pin TSSOP

28-pin TSSOP package, 4.40mm (173mil).

SkewCharacteristics:

•

CPU – CPU <175ps

PCI – PCI < 500ps

CPU(early) – PCI = 1.5ns – 4ns.

Block Diagram

PLL2

48MHz

24_48MHz

/ 2

XTAL

OSC

REF

PLL1

Spread

CPU

DIVDER

Stop

CPUCLK0

Spectrum

SEL48_24#

CPU3.3V_2.5V#sel

SEL66/60#

PD#

Control

Logic

PCI

DIVDER

Stop

PCICLK (5:0)

Power Groups

PCI_STOP#

CPU_STOP#

SDATA

VDD_Core, GND_Core = PLL core

VDDREF, GNDREF = REF, X1, X2

VDDPCI, GNDPCI = PCICLK (5:0)

VDD48, GND48 = 48MHz (1:0)

Config.

Reg.

SCLK

0540E—08/20/03

12 3 4 5 6 7...12

中文翻译

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