IC41C16100S-45KI

更新时间： 2024-01-11 20:45:20

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
21页	673K
描述
1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

IC41C16100S-45KI 数据手册

IC41C16100S

IC41LV16100S

TRUTH TABLE

Function

RAS

LCAS UCAS

Address t^R/tC I/O

Standby

Read: Word

Read: Lower Byte

High-Z

ROW/COL

DOUT

Lower Byte, DOUT

Upper Byte, High-Z

Read: Upper Byte

ROW/COL

Lower Byte, High-Z

Upper Byte, DOUT

Write: Word (Early Write)

Write: Lower Byte (Early Write)

ROW/COL

DIN

Lower Byte, DIN

Upper Byte, High-Z

Write: Upper Byte (Early Write)

Read-Write^(1,2)

ROW/COL

Lower Byte, High-Z

Upper Byte, DIN

→

DOUT, DIN

EDO Page-Mode Read⁽²⁾1st Cycle:

2nd Cycle:

→

ROW/COL

NA/COL

NA/NA

DOUT

→

Any Cycle:

EDO Page-Mode Write⁽¹⁾1st Cycle:

2nd Cycle:

ROW/COL

DIN

NA/COL

DIN

EDO Page-Mode^(1,2)

Read-Write

1st Cycle:

→

ROW/COL

NA/COL

DOUT, DIN

2nd Cycle:

→

Hidden Refresh

Read⁽²⁾

→

ROW/COL

DOUT

Write^(1,3)

→

ROW/COL

DOUT

RAS-Only Refresh

ROW/NA

High-Z

CBR Refresh⁽⁴⁾

→

Notes:

1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).

2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).

3. EARLY WRITE only.

4. At least one of the two CAS signals must be active (LCAS or UCAS).

Integrated Circuit Solution Inc.

DR010-0D 11/26/2004

1 2 345 6 7...21

下载PDF

与IC41C16100S-45KI相关器件

型号	品牌	描述	获取价格	数据表
IC41C16100S-45KIG	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41C16100S-45T	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41C16100S-45TG	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41C16100S-45TG	ISSI	EDO DRAM, 1MX16, 45ns, CMOS, PDSO44, 0.400 INCH, LEAD FREE, TSOP2-50/44	获取价格
IC41C16100S-45TI	ICSI	1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE	获取价格
IC41C16100S-45TI	ISSI	EDO DRAM, 1MX16, 45ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44	获取价格