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IBM25NPE405L-3DA200C PDF预览

IBM25NPE405L-3DA200C

更新时间: 2024-01-28 16:32:36
品牌 Logo 应用领域
国际商业机器公司 - IBM 时钟外围集成电路
页数 文件大小 规格书
48页 741K
描述
RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA324, 23 MM, PLASTIC, EBGA-324

IBM25NPE405L-3DA200C 技术参数

是否Rohs认证: 不符合生命周期:Contact Manufacturer
零件包装代码:BGA包装说明:BGA, BGA324,22X22,40
针数:324Reach Compliance Code:unknown
ECCN代码:3A001.A.3HTS代码:8542.31.00.01
风险等级:5.47其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:12位大小:32
边界扫描:YES最大时钟频率:66.6 MHz
外部数据总线宽度:32格式:FIXED POINT
集成缓存:YESJESD-30 代码:S-PBGA-B324
JESD-609代码:e0长度:23 mm
低功率模式:YES端子数量:324
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA324,22X22,40封装形状:SQUARE
封装形式:GRID ARRAY电源:2.5,3.3 V
认证状态:Not Qualified速度:200 MHz
子类别:Microprocessors最大供电电压:2.7 V
最小供电电压:2.3 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:23 mm
uPs/uCs/外围集成电路类型:MICROPROCESSOR, RISCBase Number Matches:1

IBM25NPE405L-3DA200C 数据手册

 浏览型号IBM25NPE405L-3DA200C的Datasheet PDF文件第2页浏览型号IBM25NPE405L-3DA200C的Datasheet PDF文件第3页浏览型号IBM25NPE405L-3DA200C的Datasheet PDF文件第4页浏览型号IBM25NPE405L-3DA200C的Datasheet PDF文件第6页浏览型号IBM25NPE405L-3DA200C的Datasheet PDF文件第7页浏览型号IBM25NPE405L-3DA200C的Datasheet PDF文件第8页 
Advance Information  
TM  
PowerNP NPe405L Embedded Processor Data Sheet  
NPe405L Embedded Controller Functional Block Diagram  
Clock  
Control  
Reset  
Universal  
Interrupt  
Controller  
x2  
Power  
Mgmt  
See Peripheral Interface  
Clock Timing table  
DCRs  
Timers  
MMU  
UART  
x2  
PPC405  
Processor Core  
GPIO  
IIC  
DCR Bus  
Trace  
ICU  
JTAG  
DCU  
16KB  
I-Cache  
8KB  
D-Cache  
On-chip Peripheral Bus (OPB)  
Arb  
DMA  
Controller  
(4-Channel)  
OPB  
Bridge  
Processor Local Bus (PLB)  
Ethernet  
MAL8  
x2  
MAL64  
HDLCEX  
External  
Bus  
Controller  
SDRAM  
Controller  
ZMII  
32 channels  
2 ports  
133 MHz max  
66 MHz max  
- 13-bit addr  
- 32-bit data  
- 28-bit addr  
- 16-bit data  
MII, RMII, SMII  
TM  
The NPe405L is designed using the IBM Microelectronics Blue Logic methodology in which major  
functional blocks are integrated to create an application-specific ASIC product. This approach provides a  
TM  
consistent way to generate complex ASICs using IBM CoreConnect Bus Architecture.  
Note: IBM CoreConnect busses provide:  
• 64-bit PLB interfaces up to 133MHz  
• 32-bit OPB interfaces up to 66MHz  
Address Map Support  
The NPe405L incorporates two simple and separate address maps. The first is a fixed processor address  
map that serves the PowerPC family of processors. This address map defines the possible contents of  
various address regions which the processor can access. The second address map is for Device  
Configuration Registers (DCR). This address map is accessed by software running on the NPe405L  
processor through the use of mtdcr and mfdcr commands.  
5

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