Datasheet > IBM043611TLAB-7

IBM043611TLAB-7

更新时间： 2024-02-16 06:41:26

品牌	Logo	应用领域
国际商业机器公司 - IBM		时钟静态存储器内存集成电路
页数	文件大小	规格书
22页	319K
描述
Standard SRAM, 32KX36, 3ns, CMOS, PBGA119, BGA-119

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IBM043611TLAB-7 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Lifetime Buy	零件包装代码：	BGA
包装说明：	BGA, BGA119,7X17,50	针数：	119
Reach Compliance Code：	unknown	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.84
最长访问时间：	3 ns	最大时钟频率 (fCLK)：	142.85 MHz
I/O 类型：	COMMON	JESD-30 代码：	R-PBGA-B119
JESD-609代码：	e0	长度：	22 mm
内存密度：	1179648 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	36	功能数量：	1
端子数量：	119	字数：	32768 words
字数代码：	32000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	32KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装等效代码：	BGA119,7X17,50	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	1.5,3.3 V
认证状态：	Not Qualified	座面最大高度：	2.41 mm
最大待机电流：	0.025 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.35 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1.27 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

IBM043611TLAB-7 数据手册

IBM041811TLAB

IBM043611TLAB

32K x 36 & 64K x 18 SRAM

Preliminary

SRAM Features

Late Write

Late Write function allows for write data to be registered one cycle after addresses and controls. This feature

eliminates one bus-turnaround cycle necessary when going from a Read to a Write operation. Late Write is

accomplished by buffering write addresses and data so that the write operation occurs during the next write

cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-

rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array will be

updated with address and data from the holding registers. Read cycle addresses are monitored to determine

if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array

occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last

written address will have new byte data from the write buffer and remaining bytes from the SRAM array.

Mode Control

Mode control pins M1 and M2 are used to select four different JEDEC standard read protocols. The SRAM

supports the following protocols:

• Single Clock, Flow-Through (M1 = V , M2 = V

)

• Pipeline (M1 = V , M2 = V

)

• Register-Latch (M1 = V , M2 = V

)

• Dual Clock, Flow-Through (M1 = V , M2 = V

)

This datasheet only describes Pipeline functionality. Mode control inputs must be set with power-up and must

not change during SRAM operation. Dual Clock will not be offered.

Sleep Mode

Sleep Mode is enabled by switching asynchronous signal ZZ High. When the SRAM is in Sleep mode, the

outputs will go to a High-Z state and the SRAM will draw standby current. SRAM data will be preserved and a

recovery time (t

) is required before the SRAM resumes to normal operation.

ZZR

Programmable Impedance/Power-Up Requirements

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and V to allow for the

SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line

impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a toler-

ance of TBD% is between 175W and 350W. Periodic readjustment of the output driver impedance is neces-

sary as the impedance is greatly affected by drifts in supply voltage and temperature. One evaluation occurs

every 64 clock cycles and each evaluation may move the output driver impedance level only one step at a

time towards the optimum level. The output driver has 32 discrete binary weighted steps. The impedance

update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchro-

nously switch the SRAM into and out of High-Z, triggering an update. The user may choose to invoke asyn-

chronous G updates by providing a G setup and hold about the K Clock to guarantee the proper update. In

order to guarantee the optimum internally regulated supply voltage, the SRAM requires 4µs of power-up time

after V reaches its operating range. Furthermore, 2048 cycles followed by a Low-Z to High-Z transition are

required to guarantee optimum output driver impedance.

Use is further subject to the provisions at the end of this document.

77H9965.T5

10/98

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